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The inverting circuit with the T network in the feedback is redrawn in Fig. P2.30 in a way that emphasizes the observation that R2 and R3 in effect are in parallel (because the ideal op amp forces a virtual ground at the inverting input terminal). Use this observation to derive an expression for the gain by first finding and For the latter use the voltage-divider rule applied to R4 and (R2 || R3) enter image description here

Above is the question I cant understand why i cant an Req=R2||R3+R4 in feedback circuit. But using a volatge divider considering R2||R3 and R4 to calculate Vx is valid.

  • The most simple way for finding the closed-loop gain of the circuit is to apply the star-delta conversion. In this case, one of the "new" resistors can be neglected because it appears as a load only. – LvW Jan 13 '21 at 16:41
  • I would have considered the Thévenin generator from the \$V_{out}\$ side with an output resistance \$R_{th}\$ of \$R_3||R_4\$ biasing \$R_2\$ then apply superposition. See my [answer](https://electronics.stackexchange.com/questions/539009/is-there-an-easier-alternative-for-finding-the-gain-of-this-operational-amplifie/539122#539122) on a quite similar question. – Verbal Kint Jan 13 '21 at 16:42

2 Answers2

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Hints: -

why i cant an Req=R2||R3+R4 in feedback circuit.

Your formula finds the Thevenin equivalent resistance but looking into the R4 resistor from the op-amp output node. That will be of some use in your derivation.

You also need to recognize that the Thevenin equivalent voltage at the junction of R3 and R4 is a fraction of that at the op-amp's output. So, find Vx in terms of Vout and then recognize that Vx feeds via R2 creating the negative feedback.

Or regard the op-amp output as being Vx and derive the op-amp gain to Vx (R2 as feedback) then, when you have that formula, convert it to the real op-amp output using the reverse of the attenuation made by R4 and R3||R2.

Then you are good to go.

Andy aka
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  • First of all thank you @andy I can understand why Vc is fraction of opamps output which can be shown by nodal analysis of junction at r3 and r4 Also i understood the method consider Vo=Vx and then using attenuation of R4 and R3 but I didnt understand why it works. Also I didnt understand why R2 and R3 cant be in parallel due to virtual ground at inverting terminal – NEELANSHU Garg Jan 13 '21 at 16:44
  • You are treating R2 exactly like R3 and hoping that all will be good. You can't because R3 doesn't connect to the inverting input hence your calculation would be wrong. I didn't understand where Vc comes from @NEELANSHUGarg. I think you meant Vx. – Andy aka Jan 13 '21 at 17:05
  • ya I am sorry that is a typo , its supposed to be Vx. I understood that part now. please explain why the assumption of voltage divider considering Vx=R3||R2/(R3||R2)+R4 * Vout is valid. I know I'm not very good at subject but I'm trying to understand it I am stuck with this problem for 2 days.T_T – NEELANSHU Garg Jan 13 '21 at 17:31
  • Well, can you see that at Vx the voltage will be R3||R2/(R3||R2)+R4 * Vout? BTW there isn't a minus sign in front of it. Do you have problems with realizing that as far as Vx is concerned, the virtual earth of the inverting terminal can be regarded as actual earth? Is it this that is your problem area? – Andy aka Jan 13 '21 at 17:34
  • Ya I edited the minus sign. yup i have problem with that when in above case R2 and R3 supposed to be connected similarly is not valid(explained by you in 2nd comment) but while using potential divider virtual earth and real earth are same and valid – NEELANSHU Garg Jan 13 '21 at 17:57
  • Ask yourself does the current flowing in R3 find its way to the non inverting input. Wherea when we are considering the impedance connected to the output pin, all the current entering R4 is important and who cares whether some of it goes to real ground (0 volts) or virtual ground (also precisely 0 volts). – Andy aka Jan 13 '21 at 18:52
  • Thanks you really solved my problem – NEELANSHU Garg Jan 14 '21 at 08:35
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Absolute gains shown by example (*-1)

schematic

simulate this circuit – Schematic created using CircuitLab

Tony Stewart EE75
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