0

I am confused by a litte detail with CMOS inverter. Note that I am really a beginner in CMOS "theory". Here is the electrical circuit:

enter image description here

At "first view", I understand the principle. If \$V_{in}\$ is high (\$V_{in}=V_{DD}\$), then the PMOS will be open and the NMOS closed. Thus \$V_{out}=0\$.

Reciprocally, \$V_{in}=0\$ implies the PMOS closed and NMOS closed thus \$V_{out}=V_{DD}\$

My question

I have trouble when I look at the details. Let us consider \$V_{in}\$ high for instance. A PMOS will be closed for \$V_{GS} < V_{Tp}<0\$ (threshold voltage), and \$V_{GS} > V_{Tn}>0\$ for NMOS.

But for this I must identify where are source and drain. To identify where is the source and the drain of a transistor, I must find which one has the highest voltage.

But as I do not know \$V_{out}\$ how can I find them ? \$V_{out}\$ is what I try to find so I am not supposed to know it (else the reasoning is circular)...

Is there an implicit assumption that "by design", for CMOS circuit, any voltage in the circuit will verify \$0 < V < V_{DD}\$. Applying this to \$V_{out}\$ I can deduce source and drain for both transistors and solve my issue ?

Because "in principle", I could imagine some negative voltages and because of that identifying what is source and drain is not straightforward here.

StarBucK
  • 147
  • 6
  • Use `\$\$` to make latex work properly. You drew the schematic so you label where source and drain need to be. There is a right way and a wrong way BTW. – Andy aka Jan 09 '21 at 15:55
  • @Andyaka I used $tex$ but it didn't work. I will try with the \$ – StarBucK Jan 09 '21 at 15:57
  • @Andyaka for source and drain this is actually exactly my question: aren't transistor supposed to be symmetric on the port where current flow. And that is actually the voltage difference that tells you where source and drain are ? This is really my confusion and what motivates my question. – StarBucK Jan 09 '21 at 15:59
  • No, transistors aren't symmetrical in practice. – Andy aka Jan 09 '21 at 16:00
  • 1
    `But for this I must identify where are source and drain. To identify where is the source and the drain of a transistor, I must find which one has the highest voltage.` No, to identify source and drain you must know whether you have a P or N channel device, and then source is the common terminal of the inverter that that device forms, so the two sources connected to GND and VDD, the two drains go to the output. – Neil_UK Jan 09 '21 at 16:02
  • @Andyaka I am not sure to understand. As explained here https://electronics.stackexchange.com/questions/276820/identifying-source-and-drain-terminals-for-mosfet-circuit, the source and drain play totally symmetric role in the transistor. – StarBucK Jan 09 '21 at 16:05
  • @Neil_UK I don't understand either. Your comment seems to imply that to identify source and drain of a transistor I must have an inverter structure around ? But I could also use the transistor "alone" ? Could you elaborate ? Thanks. – StarBucK Jan 09 '21 at 16:07
  • 1
    There is no ambiguity, P channel source is VDD, N channel source is GND, gates are tied together for input and drains are tied together for output. – Justme Jan 09 '21 at 16:11
  • @Justme I asked a more focused question then. I am still not understanding. https://electronics.stackexchange.com/questions/541716/identifying-source-and-drain-for-a-transistor – StarBucK Jan 09 '21 at 16:17
  • That's been closed - for the reasons given. – Andy aka Jan 09 '21 at 16:29
  • @Andyaka if a post should have been closed it should have been this one which is much less focus. The other one is focusing on the exact point I am missing and doesn't need to invoke the inverter. – StarBucK Jan 09 '21 at 16:30
  • CMOS p channel device has source at positive supply. There is nothing else to it (symmetry or no symmetry). – Andy aka Jan 09 '21 at 16:30
  • @Andyaka But aren't you assuming there are only two voltage in play: "high" and "low". What if the PMOS is plugged on one hand at Vdd/2 and on the other at Vdd/4. There is no "positive" supply in this example. Isn't your definition based on some assumption on the possible voltage you apply ? (Only Vdd and 0) – StarBucK Jan 09 '21 at 16:32
  • I have no idea what you are talking about. Let's say the p ch device is perfectly symmetrical, then it can only do the job it is intended to do if we regard the more positive terminal as the source. If you then (thought experiment) could physically swap it around, then it's still the source that connects to the more positive supply even though its been swapped around. – Andy aka Jan 09 '21 at 16:38
  • @Andyaka so isn't this exactly equivalent to what I said in my question ? The source of a PMOS if the highest voltage while the drain is the lowest. "To identify where is the source and the drain of a transistor, I must find which one has the highest voltage". Maybe my sentence was not clear enough but this is what I meant. – StarBucK Jan 09 '21 at 16:39
  • @Andyaka like I have a given transistor, the gate is easy to identify. Then I look at the two remaining port. I look at which one has the highest voltage. It will correspond to the source for a PMOS and the drain of an NMOS. All port have been identified the work is done. Would you agree? – StarBucK Jan 09 '21 at 16:40
  • 1
    Your transistor will have bulk connected to source making it asymmetrical. – Andy aka Jan 09 '21 at 16:44
  • @Andyaka Ok this is probably the knowledge I missed. Thanks. – StarBucK Jan 09 '21 at 16:45
  • With a symmetrical transistor, the source and drain are defined by how you connect and use it. – Neil_UK Jan 09 '21 at 16:54

1 Answers1

1

To identify where is the source and the drain of a transistor, I must find which one has the highest voltage.

But as I do not know \$V_{out}\$ how can I find them ? \$V_{out}\$ is what I try to find so I am not supposed to know it?

You know that the output voltage will never be greater than \$V_{DD}\$ or less than \$V_{SS}\$.

Therefore, for the PMOS device on the high side, the source is always the terminal connected to \$V_{DD}\$ and for the NMOS device on the low side, the source is the terminal connected to \$V_{SS}\$.

As others have pointed out in comments, if you're building this from three-terminal discrete MOSFETs you must properly connect the terminals designated by the manufacturer as the source and drain correctly or the body diode will conduct, and the FET will not be able to block current. If you're building the device within an IC, then you'll be able to connect the bulk terminal to the correct voltage rail, and the device will behave symmetrically, provided you don't try to drive either source or drain terminal beyond the rails.

The Photon
  • 126,425
  • 3
  • 159
  • 304
  • Thank you for the answer. Ok so the source and drain are provided by the manufacturer. The device not being symmetrical because the bulk is connected to the source (as explained by Andyaka in the comments). And "in general", the source of a PMOS must be connected to a voltage higher (or equal) than the drain. The source of an NMOS mst be connected to a voltage lower (or equal) than the drain. Would you agree with my statement ? – StarBucK Jan 09 '21 at 16:44
  • 1
    @StarBucK, yes, that's correct. – The Photon Jan 09 '21 at 16:47