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I understand that PLLs have a settling time but if I were to do a hardware modification that changes Vco of a reference clock to scale based on temperature of my CPU, would I be able to do so while the CPU is running or would the system lock due to PLL variance?

If so a corollary: what is the maximum frequency I can adjust the base clock of the PLL while the output frequency can remain marginally stable? Is it the Nyquist rate or the 1/(settling time)?

My understanding of PLLs is elementary please be gentle thank you.

Bots Fab
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    What does the data sheet say. There is no generic answer. – Andy aka Jan 07 '21 at 12:32
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    On STM32 M0+ you have to disable the PLL, change your speed and adjust your settings (PWR,Latency etc.) and then switch the PLL back on. – Sorenp Jan 07 '21 at 13:01
  • Doesn't the PC change the clock speed VS. load? In my small Linux computer I can set the minimal and maximal frequency of the CPU which is changing on demand. – Marko Buršič Jan 07 '21 at 13:31
  • Yes it has turbo, power states and multiplier. Together these set clock speed but I am looking at CPUs that have locked multipliers and overclocking past turbo speeds and max power state, both of which are calculated from reference clock and/or multiplier. – Bots Fab Jan 07 '21 at 15:04
  • Yes but there are multiple ways to do this, you can set the divisor of the PLL and the reference clock. I do not know but would assume there are many layers to clocking in modern CPUs. – Bots Fab Jan 07 '21 at 15:14
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    All depends on the system. You can design one that allows this; other systems may not. –  Jan 07 '21 at 15:50

1 Answers1

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As noted in the comment, there is no general answer to this. The answer is going to be based on your specific case. Let me, however, show you how to find what you're looking for in an example.

In this case I have taken an excerpt of a datasheet for a part that I'm familiar with, the Microchip (i.e. Atmel) ATxmega128A4U MCU. Note this page from the document at:

Microchip ATxmega128A4U Datasheet

If you look at the highlighted (in yellow) specification, it says that for this part, you cannot change the input clock period by more than 10% from one clock cycle to the next. What might happen is not specified but if you are doing it anyway, be prepared for indeterminate behavior.

I do note that the chip itself has internal selections for switching between 32MHz, 2MHz, and 32KHz clocks and there are not stated restrictions on switching these in software. So I assume that the chip designers have accommodated that somehow.

I'm going to guess that the reason for the 10% limit is that the internal PLL can only track a changing clock period so quickly and if you go beyond 10% up or down, the PLL may lose it's lock.

Microchip ATxmega Datasheet

jwh20
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