How to implement division?

Question

I'm creating an ALU for a simple calculator. I have made the addition, subtraction, and multiplication part of the ALU and with them I didn't have to initialize anything.

I am attempting to create the division part but my inputs and outputs will not initialize. I have tried setting the ports to 0 but still they remain uninitialized (it reports "UUUU" or "UUUUUUUU").

The problem seems to be in this line:

 X <=std_logic_vector(to_unsigned(to_integer(unsigned(A))/to_integer(unsigned(B)),32));

Source:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity DIV is
    port(
        A: in std_logic_vector(15 downto 0);
        B: in std_logic_vector(15 downto 0);
        X: out std_logic_vector(31 downto 0)
    );
end DIV;

architecture Behavioral of DIV is


begin

       X <=std_logic_vector(to_unsigned(to_integer(unsigned(A))/to_integer(unsigned(B)),32));
      
 
end Behavioral;

Testbench:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity DIV_tb is
end;

architecture bench of DIV_tb is

  component DIV
      port(
          A: in std_logic_vector(15 downto 0);
          B: in std_logic_vector(15 downto 0);
          X: out std_logic_vector(31 downto 0)
      );
  end component;

  signal A: std_logic_vector(15 downto 0);
  signal B: std_logic_vector(15 downto 0);
  signal X: std_logic_vector(31 downto 0);

begin

  uut: DIV port map ( A => A,
                      B => B,
                      X => X );

  stimulus: process
  begin
  
    A<= std_logic_vector(to_unsigned(integer(12), 16));
    B<= std_logic_vector(to_unsigned(integer(6), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(2), 32)) then report "PASS for division    of A = 12, B = 6";
    else report "FAIL for division    of A = 12, B = 6";
    end if;

    A<= std_logic_vector(to_unsigned(integer(300), 16));
    B<= std_logic_vector(to_unsigned(integer(7), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(42), 32)) then report "PASS for division    of A = 300, B = 7";
    else report "FAIL for division    of A = 300, B = 7";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(500), 16));
    B<= std_logic_vector(to_unsigned(integer(6), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(83), 32)) then report "PASS for division    of A = 500, B = 6";
    else report "FAIL for division    of A = 500, B = 6";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(755), 16));
    B<= std_logic_vector(to_unsigned(integer(7), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(107), 32)) then report "PASS for division    of A = 755, B = 7";
    else report "FAIL for division    of A = 755, B = 7";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(500), 16));
    B<= std_logic_vector(to_unsigned(integer(14), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(35), 32)) then report "PASS for division    of A = 500, B = 14";
    else report "FAIL for division    of A = 500, B = 14";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(222), 16));
    B<= std_logic_vector(to_unsigned(integer(11), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(20), 32)) then report "PASS for division    of A = 222, B = 11";
    else report "FAIL for division    of A = 222, B = 11";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(18), 16));
    B<= std_logic_vector(to_unsigned(integer(6), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(3), 32)) then report "PASS for division    of A = 18, B = 6";
    else report "FAIL for division    of A = 18, B = 6";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(999), 16));
    B<= std_logic_vector(to_unsigned(integer(8), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(124), 32)) then report "PASS for division    of A = 999, B = 8";
    else report "FAIL for division    of A = 999, B = 8";
    end if;
    
  end process;


end;

This an image of the wave forms:

Looks like you actually have to run the simulation. Try and find a "run" command or button. — , Jan 04 '21 at 16:07

score 0 · Answer 1 · edited Apr 05 '23 at 17:52

so it turns out the you must initialize the signals in the test bench to a value that is greater then 0. Below I left the revision of the test bench.

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity DIV_tb is
end;

architecture bench of DIV_tb is

  component DIV
      port(
          A: in std_logic_vector(15 downto 0);
          B: in std_logic_vector(15 downto 0);
          X: out std_logic_vector(31 downto 0)
      );
  end component;

  signal A: std_logic_vector(15 downto 0):="0000000000000001";
  signal B: std_logic_vector(15 downto 0):="0000000000000001";
  signal X: std_logic_vector(31 downto 0);

begin

  uut: DIV port map ( A => A,
                      B => B,
                      X => X );

  stimulus: process
  begin
  
    A<= std_logic_vector(to_unsigned(integer(12), 16));
    B<= std_logic_vector(to_unsigned(integer(6), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(2), 32)) then report "PASS for division   of A = 12, B = 6";
    else report "FAIL for division   of A = 12, B = 6";
    end if;

    A<= std_logic_vector(to_unsigned(integer(300), 16));
    B<= std_logic_vector(to_unsigned(integer(7), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(42), 32)) then report "PASS for division   of A = 300, B = 7";
    else report "FAIL for division   of A = 300, B = 7";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(500), 16));
    B<= std_logic_vector(to_unsigned(integer(6), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(83), 32)) then report "PASS for division   of A = 500, B = 6";
    else report "FAIL for division   of A = 500, B = 6";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(755), 16));
    B<= std_logic_vector(to_unsigned(integer(7), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(107), 32)) then report "PASS for division   of A = 755, B = 7";
    else report "FAIL for division   of A = 755, B = 7";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(500), 16));
    B<= std_logic_vector(to_unsigned(integer(14), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(35), 32)) then report "PASS for division   of A = 500, B = 14";
    else report "FAIL for division   of A = 500, B = 14";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(222), 16));
    B<= std_logic_vector(to_unsigned(integer(11), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(20), 32)) then report "PASS for division   of A = 222, B = 11";
    else report "FAIL for division   of A = 222, B = 11";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(18), 16));
    B<= std_logic_vector(to_unsigned(integer(6), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(3), 32)) then report "PASS for division   of A = 18, B = 6";
    else report "FAIL for division   of A = 18, B = 6";
    end if;
    
    A<= std_logic_vector(to_unsigned(integer(999), 16));
    B<= std_logic_vector(to_unsigned(integer(8), 16));
    wait for 1ns;
    if X =std_logic_vector(to_unsigned(integer(124), 32)) then report "PASS for division   of A = 999, B = 8";
    else report "FAIL for division   of A = 999, B = 8";
    end if;
    
  end process;

end;

Specifically, you need to set `B` to a non-zero value, because dividing by zero doesn't work. — Simon Richter, Dec 05 '22 at 07:00

How to implement division?

1 Answers1