0

I'm using the DSP unit (just a fancy name for the multiplier/accumulator unit) of the Gowin GW1N devices to do some fairly simple math. These units accept two 18 bit inputs for the multiplier adding the 36 bit result into the 55 bit accumulator. It also subtracts a 54 bit input from the 55 bit accumulator at the same time. I was planning to use 18 bit data in Q1.17 format. Then someone asked me if these units were signed or unsigned... I don't know. Seems that unlike addition, multiplication hardware is different for signed and unsigned numbers.

It is hard to imagine the multipliers are not signed, but I'm not sure. I guess I'll have to test them to see.

The documentation on this DSP unit is truly abysmal lacking much detail at all. However, I think I may have gleaned a bit of insight from a comprehensive block diagram in the main document combined with the simulation source code for the block in the mode I will be using. The code shows signals named ASIGN and BSIGN. Initially I had hoped they would be to control if the inputs were complemented to allow for subtraction and such, but they are for controlling the use of the sign bit.

I see logic that clearly control the sign extension of the 18 bit multiplier inputs to 36 bits. These 36 bit numbers are multiplied using the VHDL operator defined in

use IEEE.STD_LOGIC_UNSIGNED.ALL;

assigning the result to a 72 bit signal which is then truncated to the 36 lsbs.

    mult_out_tmp <= ina * inb;
    mult_out <= mult_out_tmp(35 downto 0);

It is late and my brain hurts. Is this controlling the multiplier to allow it to be used for either signed or unsigned numbers? Unsigned would be great! The subtract input allows me to subtract values without complementing them and the accumulator feedback allows values to be added through sequential load and accumulate steps. Doesn't matter how many steps it takes really. We have maybe 100 calculations to do and 167772 cycles to do them in.

Yeah, I think I need to write some test code. Is this the customary way to design FPGA multipliers, with a control to indicate if the inputs are signed or unsigned? Do I understand this correctly?

gnuarm
  • 187
  • 11
  • I have successfully used Gowin DSP blocks for signed multiplication. I can share as an answer. But you seem to prefer unsigned operands, do you? And I'm not sure, what you mean by "Q1.17 format". Anyway, maybe [this link](https://www.gowinsemi.com/upload/database_doc/8/document/5a0e570a988c0.pdf?_file=database_doc%2F8%2Fdocument%2F5a0e570a988c0.pdf#page=27) or [this one](https://www.gowinsemi.com/upload/database_doc/3/document/5bfcfde43c45c.pdf?_file=database_doc%2F3%2Fdocument%2F5bfcfde43c45c.pdf#page=58) can help you. – megasplash Jan 03 '21 at 12:00
  • Never use non-standard `std_logic_unsigned ` library. Use `numeric_std` and declare signals as `signed` or `unsigned`. That will be usually enough for arithmetic operations unless your tool screws up this. – maximus Jan 03 '21 at 17:30
  • @rakend I don't have a choice. This is Gowin supplied code. It is all slv, not signed or unsigned. I'm not going to mess with their code for simulation. – gnuarm Jan 03 '21 at 23:34
  • @megasplash, thanks for your reply. I have those documents. Yes, this code does not need signs other than in results to detect inequalities. If the result has a '1' in the msb of A×B - C, that means A×B < C (55 or 54 bit result) The real issue is that I need to understand what is happening in the multiplier and I think I got it now. I guess I'm really just looking for confirmation that they use the same hardware for signed and unsigned multiplies and the ASIGN AND BSIGN inputs control this. As I said, the docs are horrible about explaining any of this. I assume you set them both to '1'? – gnuarm Jan 03 '21 at 23:41

0 Answers0