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I've been reading about how fractional spurs can be reduced in a Digital MASH Delta Sigma Modulator (especially for application with a fractional-N PLL) by having the initial condition of the first stage be set odd (typically by just setting the LSB to 1 when the circuit is restarted).

The books/papers that come to this conclusion (Minimizing Spurious Tones in Digital Delta-Sigma Modulators by Hosseini and Kennedy and Rigorous analysis of delta-sigma modulators for fractional-N PLL frequency synthesis by Kozak and Kale) both operate on the assumption that the MASH DSM is composed entirely of first order stages (e.g. a MASH 1-1 or MASH 1-1-1); would this principle hold true for other configurations (e.g. a MASH 2-1 or MASH 2-1-1)? I haven't found any literature discussing this deterministic technique for spur reduction for other MASH configurations. If any textbooks/papers talk about it, I would very much like to know.

Jack
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This is on of those folklore things. There are very few synthesiser practitioners in the world who use fractional-N, very few of them (even those who write books) know all they need to know, and much of what has been done is shrouded in commercial secrecy, so there isn't a generally accepted answer to this in circulation.

It's quite easy to get MASH, or one of the many other algorithms, to generate a number stream suitable for driving a synthesiser. It's quite difficult to engineer a synthesiser so that the full performance of that number stream is realised.

Of the many things that can be done to make a synthesiser generate spurs are (1) failure of isolation between reference and output sections (2) use of a phase detector with non-linearities (3) use of a divider with data-dependent propagation delay. While most engineers will accept (1) and strive for isolation with buffer amplifiers, decoupling, separate screened pockets etc, a surprising number do not accept that (2) or (3) need attention too.

Any of these hardware problems can give rise to spurs that can look for all the world like defects in the number stream. Setting the LSB of the DSM input so its output is 'busier' can mask some of these effects.

In a well-engineered synthesiser, a MASH 1-1-1 can give results that are 'perfect' in the sense that the RF output is indistinguishable from that of another synthesiser using the same VCO frequencies and PLL bandwidth, but using integer multiplication from a similar reference frequency.

Since various patents in the field have expired, a lot of people are coming new to fractional-N synthesis, and blithely making errors number (2) and (3). Many will use integrated divider + PSD solutions from some major manufacturers, which integration makes it impossible to maintain adequate isolation between output and reference. This all helps fuel the folklore.

Neil_UK
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  • Thank you for the great answer; I found it a bit odd that this miraculous "setting initial condition odd" practice only appeared in one paper and one textbook (both of them basing this conclusion off the of same paper, actually!) that I found. Most of the Delta-Sigma Modulator books and papers I've consulted are primarily in the context of ADC rather than use with a frequency synthesizer and, as a result, don't speak about requirements for number stream cycle lengths sufficient for a PLL. Do you know of or recommend any sources that might describe it in greater detail in a PLL-related context? – Jack Jan 02 '21 at 21:59