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I'm designing an open source USB Type-C Switch (KVM Style), and I started to route the USB 3.x SuperSpeed+ and USB 2.x HighSpeed differential signal pairs on the PCB.

The switch will have 2 input + 1 output USB Type-C ports. The USB 3.x SuperSpeed+ signal are switched by two ON Semi FUSB340-s, while the USB 2.x HighSpeed ones using an ON Semi NL3S588.

As I don't have too much experience with routing high speed signals, I though to post a question here and ask your opinion about my PCB design attempt.

After some research, here is what I came up with:

  • the PCB will be a 4-layer one, probably with 1 mm thickness. The top and bottom layers will be signal layers, while the two inner layer will be ground planes

  • the differential signals will be routed on both on the top and bottom layers. According to PCBWay's online calculator, a micro-strip track width of ~0.23 mm with ~0.14 mm spacing should provide about 45 Ω single / 90 Ω differential impedance

  • the two tracks of each differential pair is length matched

  • no length matching between multiple differential pairs

  • clearance between the differential pairs is kept > 1mm (~5x track width)

This is what the USB 3.x and USB 2.x signals would look on the PCB:

enter image description here

(The PCB is about 40 x 50 mm. The two symmetrically places IC-s are the FUSB340-s, while the middle one is the NL3S588. Colors are Top:red, Bottom: green, Inner layers: yellow & magenta)

Now, I have some concerns mainly related to the following areas:

  • Vias - as there are many track to route, some vias on the differential pairs (2+2 at most) where inevitable - Is 2+2 vias acceptable on a USB 3.x (~5 GHz) differential pair?

enter image description here

  • Pair swap / flip - in some cases the two signals of the differential pair were in the "wrong order", so I must swap them to be able to route them to their destination. I did this using two vias on one of the singals. - Is this the correct solution?

enter image description here

  • Top & Bottom layer tracks crossing - I guess is not a problem, as there are two ground layer between them - Is this correct?

enter image description here

  • Differential pair length matching - when trying to match the length of the tracks in the differential pairs, I observed that KiCad refuses to insert "corrections" if they would be "too small" (but the skew is still > 0.1 mm). I tried to workaround this by adding "corrections" manually. - Is this OK, or there are some special rules I should follow?

enter image description here

(left: KiCAD, right: manual)

What do you think about the above concerns?

Any other thing terribly wrong with my design? Any other observations?

Thanks!

Update:

Here is a new PCB layout with the following changes

  • re-arranged some signals between the channels of the high-speed mux to better match the layout of the USB Type-C ports
  • removed pairs swaps / crossings, by swapping the signals in the schematics
  • re-routed all the signal on the PCB - the layout looks betters, and there are max 2+2 vias on any of the singal pairs
  • moved all components to the top layer
  • adjusted the skew tuning parameters to more reasonably sized pattern enter image description here

What do you think?

bluetiger9
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  • 1) Minimize vias - sometimes USB chips support lane polarity and pair swaps so in some documents they say vias are not needed due to swaps. 2) no pair crossing like that, vias must be balanced so both pairs have equal vias 3) Check USB specs and manufacturer application notes how much imbalance can be accepted, they provide very good and practical info – Justme Jan 01 '21 at 11:36
  • 2) You're right. Looks like the USB 3.x support lane polarity inversion by spec. So, no swaps needed. 1) Some vias are still needed, because of the footprint layout of the FUSB340. I will try to minimize them. 3) USB 3.x signals should be matched to <= 5 mils (0.13 mm). That was trying to target. – bluetiger9 Jan 01 '21 at 11:58
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    It would make more sense in USB terminology to refer to 'upstream' and 'downstream' ports, rather than 'inputs' and 'outputs'. The way you've written it now it seems like you're building a device to connect 2 sets of input devices (keyboard/mouse/whatever) to a single host PC, but I'm not sure that's what you actually intend. – brhans Jan 01 '21 at 16:25
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    The intention is to connect two PC-s (1 laptop + 1 desktop) to an USB Type-C capable monitor. The monitor also has a USB hub, which will have the keyboard and mouse connected. The switch could be used for other use cases too. – bluetiger9 Jan 01 '21 at 16:43
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    Note that you can set the differential pair matching "wave" amplitude in KiCAD (right click to open menu when the matching tool is active). Making it shallower will keep better impedance matching and allow you to more accurately match the lengths. – jpa Jan 01 '21 at 19:17
  • @jpa, after some googling I found those settings too :) – bluetiger9 Jan 01 '21 at 20:19
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    It's 2021 and there are very few monitors that support USB-C or DisplayPort MST daisy-chaining, very few MST hubs, and the few USB-C hubs that exist don't support DP alt mode so you can't use them with monitors. Oh, and all of the aforementioned are unreasonably expensive. So this product, if you can make it work, would be quite welcome in hopefully shaking up the industry and finally enabling the USB-C everything we've been promised since 2017. I'm interested in what sort of cost you're targeting for a prototype? – Ian Kemp Jan 02 '21 at 21:51
  • The components cost about $15 in single quantities. The 4-layer impedance controlled PCB is $5 for 5 pcs ($1 / pcs) at JLCPCB. To these some shipping cost are added. Anyways, the cost looks pretty reasonable compared to what existing USB Type-C switches are priced at. – bluetiger9 Jan 03 '21 at 10:22

2 Answers2

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I have several suggestions.

  • First up, I would not swap the P and N over in the way you have shown. All via crossings must be symmetric, so dropping one half of the pair to the other side is a bad idea.

    If you can't curl the pair in from the opposite side of a set of pins (not possible for QFNs), then you have to do it by crossing over both P and N to the other side of the board. Here is an example of how you can reverse the P and N symmetrically. You will additionally need a pair of vias to get both traces back to the top side.

    Symmetrical Reversal of P and N

  • When crossing the pair to the other side of the board, something which you should try to minimise, you should additionally have stitching vias nearby to ensure that return currents can swap between reference planes.

  • Crossing traces over each other when there are reference planes between them is perfectly fine as you suspected.

  • For phase matching of the P and N parts of the pairs, you need to keep the changes in spacing to a minimum to avoid large impedance discontinuities. The large humps that KiCAD has made for you are terrible and should not be used. You also want to do this matching as close as possible to where the shift occurs - that means matching each individual bend, not having one big correction part way along the pair.

    As a general rule, you want to try and keep the change in spacing to around 1.25x the normal spacing, and certainly no more than 1.5x. If we assuming a 1.5x spacing, then at each 45 degree bend you need four wibbles, two each side of the bend. For example, this is a 90 degree bend, matched using eight wibbles:

    Wibbly Trace

  • As a passing note, you have lots of places where the traces cross over and then cross back again in an attempt to untangle the routing. I would suggest having another go at laying this out.

    I would look to try and keep the muxes on the same side of the board initially as it will reduce assembly costs (single side assembly is cheaper). Start with routing of the high speed traces, ignore the USB 2.0 lines initially (they are much more forgiving). You could draw thet traces initially as single-ended sketches on the silk layers to get an idea of where each trace will go (much easier to move around a silk line than a diff pair).

    Another helpful think to consider is that you may be able to reduce the cross-overs by swapping the two outputs of the mux. If you swap both RX1<->RX2 and TX1<->TX2, then it may help reduce congestion. You can compensate for this by adding a simple inverter (e.g. SN74LV1T34) to the select signal of the multiplexer.

    Similarly, the differential pairs use CML, which is a symmetrical standard. There would be no issues swapping the + and - lines of all the inputs and outputs on a multiplexer if it made it easier to route and avoided having to cross over the Ps and Ns.

    (With the device you've selected, as far as I can tell, it's a high-speed analogue mux. There doesn't appear to be any difference between the Tx and Rx signals (essentially two identical muxes, one used for Rx, one used for Tx). So you could for example use one of these muxes for both sets of transmit lines, and the other for both sets of receive lines. I'm not sure that will help you, and I would avoid doing it without checking with OnSemi first, but in a tight spot I might consider it).

Tom Carpenter
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  • Do you know of a simulation of these small "wibbles" you show here? My gut feeling is that the influence on the phase is smaller than the additional length of the trace. – asdfex Jan 01 '21 at 13:25
  • @asdfex There are a number of academic papers on such things (e.g. https://ieeexplore.ieee.org/document/7975478 - don't know if you have institutional access) – Tom Carpenter Jan 01 '21 at 14:07
  • This particular IEEE flavor I can't access. Thanks anyway! – asdfex Jan 01 '21 at 14:20
  • @TomCarpenter, I'm trying a PCB re-design with the tricks suggested. First, the channels of the muxes can rearranged, so that matches the pinout of the connector. Then, the USB 3.x seems to supports lane polarity inversion, so swaps/crosses are redundant. I will get back with an update when I'm done. – bluetiger9 Jan 01 '21 at 14:49
  • @TomCarpenter, I updated the question with the new PCB design. I wasn't able to access that academic paper you linked. So, for skew tuning I ended up using a method described in TI's "General High-Speed Signal Routing" document. It uses a 2 x spacing, on lengths of 3 x the track width. https://imgur.com/a/abuYMOU – bluetiger9 Jan 01 '21 at 20:33
  • @bluetiger9 the new design looks to be much improved. I'd still add some stiching vias around your high speed traces and beside each of the via pairs that take the high speed traces to the other layer. – Tom Carpenter Jan 02 '21 at 09:21
  • @TomCarpenter, sure I plan to add ground plane vias later. – bluetiger9 Jan 02 '21 at 10:09
  • I'd appreciate some clarification on your point about "stitching vias". With a single-ended signal, stitching vias make sense to me. However, with a differential signal, I don't see the point. – banjoeschmoe Feb 03 '21 at 00:34
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One quick thing to note is that edge-coupled diff pairs are coupled very loosly. Rather than focusing on keeping the spacing between pairs consistent what is more important is keeping each individual strip-line happy. That means ground return vias on each layer change. On top of that what you care about with length matching is time matching the pairs so they both reach your target within the data valid window.

dariomuller
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