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Currently I'm planning on doing a PCB with DDR3 memory and an Artix7 FPGA. During my research a few questions accumulated.

When looking at the reference manual of the Arty7 board, I see that I have to configure DDR3 output drive strength and On-die termination to RZQ/6. Using a 240 Ohm reference resistor, RZQ/6 equals 40 Ohms. On the other hand, the manual states, that all traces are 50 Ohm traces (100 Ohm differential) and that the FPGA's termination should be configured to 50 Ohms. Another thing is, that the Address/Control signals are all terminated with 40 Ohms according to the schematic.

The schematic of the arty7 board can be found here. The DDR3 memory and its 40 Ohm termination resistors are shown on page 9.

To me, it would be more logical to use 40 Ohms everywhere. Why is this impedance mix used? I know, that for higher speed DDR3 applications 40 Ohm systems are typically used. However, to me, it seems completely unlogical to go with 50 Ohm traces, when you can't even configure the ODT to 50 Ohms: RZQ/6 = 40 Ohms, RZQ/4 = 60 Ohms, assuming 240 Ohm RZQ. (I've never seen another value besides 240 Ohms).

  1. Can someone clarify this impedance stuff?

Technically, the DDR3 device using 40 Ohm output impedance on a 50 Ohm trace and load should't affect signal integrity, but affects the signal amplitude.

  1. Don't you get overshoot when driving a 50 Ohm net with a 40 Ohm driver?

  2. How is signal integrity guaranteed, when using a 50 Ohm line impedance in combination with 40 Ohm termination resistors?

For my design I initially intended to use 40 Ohm traces, 40 Ohm termination resistors on address lines and an ODT setting of RZQ/6. for a 1000Mb/s transfer speed DDR3 device. Unfortunately, this is a hobby project and I don't have access to SI simulation tools to verify this using the IBIS models.

GNA
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    One disadvantage of 40 ohm traces is that they will be wider than 50 ohm traces, for a given stackup. When you have a wide memory bus to route, this can really add up. As for why 50, I think it's just board houses wanting to go with what they're familiar with. – mng Jan 02 '21 at 01:07
  • Yes. I know, that 50 Ohm are more "standard" and thinner than 40 Ohm traces. But I'm still confused why the Arty 7 board uses 50 Ohm lines and a 40 Ohm termination. The second problem is with the bidirectional lines using ODT: The FPGA is configured for 50 Ohm and the DDR Memory for 40 Ohm using 50 Ohm traces. This is actually kind of confusing to me. – GNA Jan 03 '21 at 18:39
  • As you said, you get overshoot - a small amount - with a 40 ohm driver and a 50 ohm transmission line. This is by design, as that small amount of overshoot comes with slightly faster rise and fall times, which is desirable, usually. – SteveSh Jan 03 '21 at 20:36
  • How about the other direction? From FPGA to RAM on data lines. With a 50 Ohm line and a 40 Ohm ODT you will get the opposite effect. – GNA Jan 03 '21 at 20:40
  • When you're going from the FPGA to the RAM, the RAM driver output and its associated 40 ohm resistor should be disconnected from the line. – SteveSh Jan 03 '21 at 21:17
  • Yes. The driver is disconnected. But the 40 Ohm on die termination is connected instead. Usually both the ODT and the drive strength is configured to 40 Ohms (RZQ/6), which results in a 50 Ohm driver and trace driving a 40 Ohm load. Furthermore the address and command lines on the arty 7 board are explicitly terminated with 40 Ohm resistors. Which makes no sense to me, when using a 50 Ohm driver and trace. – GNA Jan 03 '21 at 21:20
  • @GNA Nice question, I don't know why manual state that! but still I had same problem and checked out ZC702 Eval board. ZC702 uses 40Ohm traces for PS DDR3 memory – pazel1374 Jan 07 '21 at 19:42
  • @pazel1374 Thanks for the info. I will check out this board as well. – GNA Jan 07 '21 at 20:24

1 Answers1

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Intel spec

Table 4-8: General Layout Guidelines DDR 2,3,4

Guidelines

Parameter

• All signal planes must be 50-60-ohm, single-ended, ±10% • All signal planes must be 100-ohm, differential ±10% • All unused via pads must be removed, because they cause unwanted capacitance

Impedance

DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines Altera Corporation

Lower impedance demands excessive wide tracks or too thin PCB is only 2 layers for height to width ratio of dielectric H/W.

3.6V logic is a 25 ohm driver +/-25% typ so 40 Ohm was sometimes used to reduce risetime slightly. PCB tolerances for Zo are typ 10% if certified with Electrical TDR tests on a test coupon then D Codes are scaled to suit the batch to guarantee tolerances otherwise they can be greater.

Here you can see the effects of a few combinations of 50 ohm traces but different source and loads. I added some lead inductance of 1nH + 1pF for ~ 1 to 1.5 mm over a ground plane.

enter image description here

Tony Stewart EE75
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