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I am trying to analyze a transistor circuit. I should find RMS output and input current and voltage. I have made some calculations but I am not sure of whether they are acurate or not.

for input RMS current:

$$ -I_{in} + I_b + \frac{V_{R1} - V_{CC} }{R2} + \frac{V_{R2} - 0}{R_1} = 0 \\ I_{in} = 4.79\mu A $$

$$ I_{in(rms)} = \frac{I_{in}}{\sqrt 2} = 3.38\mu A $$

For output voltage: I thought the voltage gain is around 3.9 so the output voltage should be Vin.Av and it is 1.14V or 1.17V.

For input voltage: My signal generator's amplitude is 300mVp so the input signal amplitude should be same.

For output current: the output current should be \$\beta.I_b\$. Thus \$I_{output} = 1.392mA\$

Here the circuit

enter image description here

Ib = 4.8 micro ampere.

hfe(beta) = 290

Signal generator: Vp = 300mV f = 400Hz

Mitu Raj
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Piko
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  • Does this answer your question? [BC547 base current and collector current](https://electronics.stackexchange.com/questions/539301/bc547-base-current-and-collector-current) – Hearth Dec 27 '20 at 17:01
  • @Hearth Yes, I use different simulation tools. I should use proteus but I use also multisim to see different. Also curcuits is different. For this circuit, there is no CE capacitor. – Piko Dec 27 '20 at 17:04
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    your voltage gain is approx R3/R4 and you may find more ways to measure and tune any cct here. https://tinyurl.com/yc6hdm99 – Tony Stewart EE75 Dec 27 '20 at 17:26
  • @TonyStewartSunnyskyguyEE75 Thank you so much for this useful tool. I added a RMS current shower but its value is always zero. – Piko Dec 27 '20 at 17:45
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    @Piko Is C1 missing? The RMS of the output will be quite different if you include the DC bias present at the collector, without a capacitor there. With the capacitor, you can get a reasonable RMS output value. So is it missing from the diagram? Or are you expecting to calculate an RMS output that includes the DC bias? – jonk Dec 27 '20 at 19:46
  • @Piko I show 6 more methods of probing either RMS or Vpp, Vmax, Vmin (which always includes DC+AC) then AC coupled to 1M to get AC Vrms, and I created a slider for SigGen for Vp max from 10mV to 1.414, https://tinyurl.com/y9g2oyem Note the 5 output floating trace has Cap offset voltage. Note the difference in Vmax-min /Vavg = THD from the asymmetry of gain as it is proportional to large-signal current that modulates DC current. This can be reduced with max gain *with bypassed Re* then reduction using negative feedback collector to base for the optimal design linearity. – Tony Stewart EE75 Dec 27 '20 at 20:15
  • max gain *with bypassed Re* then reduction using negative feedback collector to added base Rb for the optimal design linearity. Then expect ~50% of the R ratio for AC gain = 50% * Rcb/Rin as not enough open loop gain compared to Op Amp for full gain – Tony Stewart EE75 Dec 27 '20 at 20:18
  • @jonk I shouldn't use any capacitor at output. I guess you are right, I should calculate the output RMS current with DC bias. I think it is easy because the output RMS current is hfe.Ib + Iin(RMS) . I also thought maybe I can use superposition to calulate the input current ? Can I use ? – Piko Dec 28 '20 at 07:39

1 Answers1

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It's a lot easier to read the schematic, as follows:

schematic

simulate this circuit – Schematic created using CircuitLab

You are supposed to determine:

  1. \$V_{\text{B}_\text{RMS}}\$ (at the BJT base, not at the signal source -- includes a DC bias.)
  2. \$I_{\text{IN}_\text{RMS}}\$ (as seen by the signal source -- no DC bias included.)
  3. \$V_{\text{C}_\text{RMS}}\$ (at the BJT collector -- includes a DC bias.)
  4. \$I_{\text{E}_\text{RMS}}\$ (as seen by the BJT emitter -- includes a DC bias.)

(All voltages above are referenced to the schematic ground.)

I would have imagined that you were supposed to find \$V_{\text{OUT}_\text{RMS}}\$ (as shown in the schematic) because it does not include a DC bias and is therefore usually more comparable. I would also have imagined comparing it with \$V_{\text{IN}_\text{RMS}}\$. But, I guess, that's not what you are supposed to do. (The emitter current will also include its DC bias, as well. So I'll just cave in and believe two of your requirements as stated.)

Specifications are as follows:

  • \$V_{\text{IN}}=300\:\text{mV}_\text{PK}\$, \$f_\text{IN}=400\:\text{Hz}\$
  • \$h_\text{FE}=290\$ (though I can't tell if this is a specification or an observation you made)

From Nexperia's BC846 series datasheet, I find they specify the part into two \$h_\text{FE}\$ groups: A and B. The \$h_\text{FE}\$ group B says that \$200\le h_\text{FE}\le 450\$ with the typical \$h_\text{FE}= 290\$. Since that typical value from Nexperia just happens to match the number you gave, I'll assume that's where it came from.

The geometric mean is \$\sqrt{200\cdot 450}=300\$ and this means to me that \$h_\text{FE}\$ varies \$\pm 50\%\$ around \$h_\text{FE}=300\$. (Assuming the difference is intentional, there's probably a slight bit of kertosis to the almost-Gaussian distribution that accounts for the typical value being \$h_\text{FE}= 290\$.)

I don't derive the equation for it, but you can find the collector current sensitivity equation here:

$$\begin{align*} S^{I_\text{C}}_{\beta}=1-\frac{\beta}{\beta+1+\frac{R_\text{TH}}{R_\text{E}}} \end{align*}$$

In your circuit's case, this is \$\%\,I_\text{C}=S^{I_\text{C}}_{\beta}\cdot \%\,h_\text{FE}\approx \pm 3.68\%\$. So all of your calculations will need to anticipate that collector current variation.

If you include resistor tolerances of say \$2\%\$, then this gets very close to \$\%\,I_\text{C}\approx \pm 4\%\$ due to part variations.

This still avoids issues of temperature as well as part variations of \$V_\text{BE}\$ vs \$I_\text{C}\$. And those will also have an impact on the collector current variation. Depending on the temperature range you want to accept. If you go with the datasheet's total span from \$-55^\circ\,\text{C}\$ to \$150^\circ\,\text{C}\$, then this might be an added \$\pm 10\%\$ or more. So now you might be as much as \$\pm 15\%\$!

Just be aware. There's no point writing down the quiescent collector current with any higher precision than the expected situation allows for.

My thoughts:

  1. The signal generator's output impedance isn't specified. One might choose to assume an ideal signal generator. But from your writing, my gut tells me this isn't the case. So it may be \$50\:\Omega\$, or it may be something else as signal generators often have more than one output impedance available to them.
  2. \$C_2\$ will present a small but significant impedance at \$f_\text{IN}=400\:\text{Hz}\$.
  3. \$V_{\text{B}_\text{RMS}}\$ will be loaded down by \$R_1\$, \$R_2\$, and \$R_4+r_e^{'}\$ (seen through \$h_\text{FE}+1\$). It might also be loaded down further by \$r_o\$ (and inconsequentially by \$R_3\$) if the Early Effect is accounted for.
  4. \$V_{\text{B}_\text{RMS}}\$ will include a DC bias, which will have a very significant impact on the resulting calculation.
  5. \$I_{\text{IN}_\text{RMS}}\$ will be driving the entire input load, but it will not have a DC bias impacting the calculation due to \$C_2\$'s presence.
  6. \$V_{\text{C}_\text{RMS}}\$ will also include a DC bias, which will also have a very significant impact on the resulting calculation.
  7. \$I_{\text{E}_\text{RMS}}\$ will yet again include a DC bias, which will yet again have a very significant impact on the resulting calculation.
  8. The AC component of \$V_{\text{C}}\$ will have to account for the attenuation of the input signal due to the effective impedance divider at the BJT base input node. It will also have to account for the effect of \$r_e^{'}\$. It may also have to take into account \$r_o\$ if the Early Effect must be accounted for.

At this point, I cannot add much to help out as I really don't know enough about the situation, yet. If you add more to the discussion, I may add a few more thoughts to the above.

jonk
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  • Thank you so much for all this useful calculations and point of views. I guess I don't need to calculate tolarances or changing due to temperature but, I am sure of these all knowledges will help me when I make my future job. From your calculations, I should calculate VBRMS with DC bias and I can do it by IinRMS.hfe + IbDC.hfe Due to calculate the IinRMS, I can use superposition. IERMS will almost same with Iout so Ib.hfe + IinRMS.hfe. VBRMS will be VppRMS + VDCth I also shouldn't use C1 capacitor. Please let me know if I am on right way. – Piko Dec 28 '20 at 08:15
  • @Piko The DC component will vary with the quiescent point, which itself will vary with the parts and their respective variations when you build it. You cannot avoid this variation when including both DC and AC in the RMS result, sadly. That's why the DC component is almost ***never*** used in these calculations (at least, not for AC coupled stages, anyway.) However, you can calculate a theoretical value (which won't match a Spice output, so all you can do is have someone else check your work.) You write about using \$h_\text{FE}\$, but I won't be able to judge until I see how you apply it. – jonk Dec 28 '20 at 21:54
  • I added my calculations as pdf. If you have time for verify, I would be happy. https://we.tl/t-IVbq6slc7g – Piko Dec 29 '20 at 08:04