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I've some experience with Xilinx FPGA generating 10Gb/s over SMA loopback with on-off keying modulation (what scope shows) to perform BER test but the documentation shows it uses a reference clock in MHz level.

How is it possible to generate gigabit line rate especially 10Gb and above with MHz reference clock? Someone told me to look at SerDes but I could not make sense with it. Can somebody please navigate me?

JRE
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LifeIsBeatiful
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    [Phase Locked Loop](https://en.wikipedia.org/wiki/Phase-locked_loop) might be the key phrase here. – Andy aka Dec 27 '20 at 16:32
  • @Andyaka is it the only possible solution? – LifeIsBeatiful Dec 27 '20 at 16:33
  • It's the most common solution I believe. Pretty much universally recognized and used. Well, the universe is a big place and maybe on an exoplanet surrounding a star in the andromeda galaxy they use something else. – Andy aka Dec 27 '20 at 16:34
  • all RF clocks are VCO’s divided by a precalar then std variable divider to match the Xtal reference. i.e. PLL with a VCO but in Andy’s inverse it might use a quark resonator. – Tony Stewart EE75 Dec 27 '20 at 16:51
  • I believe a delay-locked loop can also be used to multiply a clock, but I have no idea if it's common or even a good idea. – Austin Dec 27 '20 at 17:20
  • Overall, the problem with this question is that you're attempting to do something moderately advanced and esoteric, without being familiar with more basic aspects of FPGA design or communications testing. This probably indicates that it would be useful to have some clarifying conversations with whoever assigned these tasks. – Chris Stratton Dec 27 '20 at 17:50
  • not only is a pll used but there are semi-standard or lets say commonly used reference clocks for various speeds I dont remember off hand the one for 10G maybe 312.5Mhz? this is no different really than how your 3ghz x86 computer runs off of a 100mhz or similar reference clock. – old_timer Dec 28 '20 at 13:59

2 Answers2

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As mentioned in comments, the transceivers in FPGAs (and elsewhere) usually use a [phase-locked loop] to generate a high frequency clock that is phase-locked to the lower-frequency reference clock.

Very roughly, that means they have a high frequency voltage-controlled oscillator (VCO). They divide the output of the VCO with a clock divider circuit. They then compare the phase of the clock divider output with the phase of the reference clock. If the clock divider output is running a little ahead or a little behind the reference clock, they adjust the control voltage of the VCO to compensate.

This generates an output clock that is a multiple of the reference clock equal to the divide ratio in the feedback path divider.

More elaborate circuits can do "fractional division" to produce an output clock that is a rational number multiplied by the reference clock instead of an integer multiple.

The Photon
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  • Yes in general conceptual terms, but in practice I don't think FPGA clock blocks are really classic analog PLL's - they fill that role by a not unrelated mechanism (eg, more of a DLL than a PLL). However some communications gear would use an external clock module locked to a low frequency reference and feeding a lower phase noise clock input into the FPGA than its internal solutions could provide. – Chris Stratton Dec 27 '20 at 17:43
  • @ChrisStratton, The first Xilinx SerDes used a DLL structure instead of PLL. But more recent ones (Virtex/Kintex/Artix-7 generation, and the one before, IIRC) use PLLs. You're right the control mechanism is probably the "bang-bang" or Alexander digital design rather than an analog filter. I'll edit to clarify. – The Photon Dec 27 '20 at 17:48
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High speed serializers use phased-locked loops (PLLs) or frequency-locked loops (FLLs) to convert a low-frequency reference clock up to the required frequency, which is usually half of the line rate. This is almost universal for a number of reasons.

First, serial line rates need to be rather precise (ppm) so that clock-data recovery can work, and it is rather difficult to make a precision oscillator at many GHz - oscillators at that frequency tend to be either tunable (and hence will be locked to a low-frequency reference...with a PLL) or not particularly precise (percent instead of PPM). Using PLLs also means that a single high-precision oscillator can be used as a reference for many different transceiver channels, even running at different rates.

Additionally, having a reference oscillator at line rate is going to produce all sorts of EMI. Running high frequency signals all over the place can also consume a lot of power, as opposed to generating it near where it is to be used. Not to mention all of the additional constraints for high-frequency design (placement, routing, impedance control, etc.).

Using a PLL also means that changing the line rate is very simple and usually can be done by simply changing some divider settings, which can be done at run time. This permits Ethernet interfaces to easily switch between 1G (1.25 Gbps), 10G (10.3125 Gbps), and 25G (25.78125 Gbps) rates, PCIe to switch between 2.5, 5, and 8 Gbps, etc. Providing separate oscillators for each required line rate would significantly increase the cost and complexity.

The PLL works by using a VCO (or other tunable oscillator) to generate the high frequency, then dividing both the output and the reference, filtering, comparing the two using a phase and frequency detector (PFD), and then continuously adjusting the VCO tuning voltage so that the divided output tracks the divided reference. This has the effect of scaling the reference frequency by a rational fraction. Since the output is locked to the reference, the output frequency will have the same precision as the reference frequency over long time scales.

alex.forencich
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