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What will be the output voltage from the opamp when one end (non-inverting terminal) is open? (For circuit see the attached figure.)

enter image description here

The way I was trying this question was like this:

For any arbitrary value of \$R\$ (resistance between point B and D) in given circuit voltage at point B is zero and due to virtual ground voltage at pt. A is also 0. Now we can apply KCL to get output voltage, and in this way can I conclude that output voltage will remain same even if circuit is open (as shown in figure?)

JRE
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Barry
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4 Answers4

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The opamp will not work because the transistors will not be able to draw their input bias current.

The first stage of an opamp is a differential pair.

diff pair

source

The inputs of the opamp are connected to the gates of Q1 and Q2. The transistors need to be able to draw current through the gate to work. If one of the inputs is open, one of the two transistors will not function properly. Thus you need to ensure that their is a DC path for both opamp inputs.

user110971
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  • OK. Got it. But suppose if in given figure there is a resistance R between point B and D and if we keep increasing this resistance then output voltage will not change. although i can solve and prove it but I don't understand it intuitively,can you elaborate that point? –  Dec 26 '20 at 10:13
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    @Barry The output will change. The input bias current will cause a small voltage to develop across the resistor. As the resistance increases said voltage will also increase, causing an offset at the output. – user110971 Dec 26 '20 at 10:25
  • "The transistors need to be able to draw current through the gate to work"?!? And where will this current flow? – Circuit fantasist Dec 26 '20 at 12:00
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    It looks like you might have a schematic of a MOSFET differential pair but your words sound like you are talking about BJTs. – Elliot Alderson Dec 26 '20 at 13:14
  • @ElliotAlderson FETs also draw current as the output changes. You need to charge the gate capacitance. – user110971 Dec 26 '20 at 13:16
  • @Circuitfantasist it will charge the gate capacitance. – user110971 Dec 26 '20 at 13:18
  • But this current is not an "input bias current". I think you have conflated your transistor types. – Elliot Alderson Dec 26 '20 at 13:28
  • @ElliotAlderson Analog disagrees. Fifth line on the [ADA4625](https://www.analog.com/media/en/technical-documentation/data-sheets/ADA4625-1-4625-2.pdf) datasheet: “low input bias current”. – user110971 Dec 26 '20 at 13:33
  • @ElliotAlderson Also keep in mind that an insulated gate does not have infinite resistance. There is still current flowing. – user110971 Dec 26 '20 at 13:35
  • Regarding the ADA4625, you have now also conflated the JFET and the MOSFET. Sigh. – Elliot Alderson Dec 26 '20 at 13:44
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    @user110971, Your ovservations are interesting... and very sophisticated ... but here we are talking about basic principles. Why should we look for current where there is no current? And why not show it where it exists in principle? Indeed, your explanations are intended for a BJT stage... – Circuit fantasist Dec 26 '20 at 13:55
  • @Circuitfantasist I’ll give it one last shot. Let’s say you have a FET input stage. When you apply power to the opamp the differential pair output will start to swing. For this to happen the FETs input capacitance needs to be charged to the appropriate level, otherwise the transistors will remain off. For the input capacitance to charge, you need a path to the power source. If one of the inputs is open, the corresponding input transistor will remain off. In any event, the circuit will not operate as desired. – user110971 Dec 26 '20 at 14:04
  • @user110971, Really, very interesting explanations... I like this way of reasoning... and I also think in this way... But, as Elliot also said above, here we are talking about input bias currents... and they are constant. So we should not talk about such changing through time currents... like in a differentiating circuit. But I do not want to impose my opinion. I would be interested to hear any objections... ... and learn something new from you ... – Circuit fantasist Dec 26 '20 at 14:14
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    @Circuitfantasist The gate oxide of a MOSFET isn't perfect either, there will always be leakage current through it, even if it's tiny. – Hearth Dec 26 '20 at 14:57
  • @Hearth, I agree that there are leakage currents... but they are not vital to the operation of MOSFET in this case. They are not controlling... the voltages are controlling. – Circuit fantasist Dec 26 '20 at 15:15
  • I think an explanation which would fit well with reality and with a wide range of abstractions would be to say that many circuits will behave as though small amounts of charge may arbitrarily unpredictably flow between any node and "the environment". Such charges will be small enough to be completely dominated by any "deliberate" transfer of charge, but properly designed circuits should be designed to be tolerant of them. A node with no deliberate current source or sink, however, may be affected by such currents. – supercat Dec 27 '20 at 00:37
  • While it may seem strange to describe things in terms of "the environment", it's not uncommon for voltages on floating nodes to be affected by e.g. waving one's hands near them. While the effects of such "hand waving" might be more accurately described in terms of shifting electromagnetic fields than charge transfer, the effects would generally be consistent with either explanation. – supercat Dec 27 '20 at 00:44
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I have long been convinced that such fundamental issues are best clarified through simple conceptual circuit diagrams in which power supplies and current paths are shown. I have done this in another question and answer from which I will use some figures here.

The problem comes from the unusual bias technique used in the input differential stages of operational amplifiers. I hope you understand very well the idea of the bias voltage - it is just another pre-existing input voltage. From this viewpoint, 1-input amplifiers are actually 2-input summing amplifiers.

The biasing is made from the side of the output - transistor emitters, where a current source (sink) is inserted. This source forces transistors to adjust their base currents so that each of them passes 1/2 of the emitter current. For this purpose, the bases should be firmly fixed (like in the case of the common-base amplifying stage). Figuratively speaking, the emitter current source "moves" the emitter voltages like by levers... so the other ends of the levers should stay immovable. And if some of the bases is not fixed at a constant voltage, the emitter source will not do anhything.

Note that there are not internal paths for the input bias currents. Circuit designers rely on an external "galvanic" (low-resistive) connection that we, consumers, should provide. Usually, input voltage sources (if they are galvanic) pass the bias currents through themselves. If not, additional relatively high resistors should be connected between the inputs and ground.

Let's look at the picture where the currents are representad by closed paths (loops). The currents are distributed symmetrically in half and the output voltages are equal.

If you disconnect T1's base, IB1 will dissapear and all the emitter current will be steered to T2. VOUT1 will reach V+ and VOUT2 will be close to ground - Fig. 1.

Differential pair without RB

Fig. 1. Differential pair without RB.

The input bias currents "create" voltage drops across the input resistances - Fig. 2.

Differential pair with RB1 and RB2

Fig. 2. Differential pair with RB1 and RB2.

Circuit fantasist
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It depends on the internals of the opamp. Here is a LM328 as an example. Q1, Q4 require some base current to function.

enter image description here

If Q1 base is disconnected, Q1, Q2 will be off. 6µA current from current source will flow through Q3, turning off Q10, turning on Q11,Q12, and output will swing to the negative rail.

Datasheet also mentions this:

enter image description here

This gives you an idea of the base currents for Q1, Q4. Since input transistors are PNP, input base current flows out of the chip. If they were NPN, it would be the other direction. If they were FETs, then input current is mostly leakage, and its polarity depends on what's happening in the chip. If it has a dual input stage like in a rail to rail opamp, then input current polarity depends on the sum of the input current for both stages, so it can flow in either direction.

suppose if in given figure there is a resistance R between point B and D and if we keep increasing this resistance then output voltage will not change.

No, that's not true. The opamp inputs source or sink bias and offset currents (source or sink depending on polarity). These currents will create voltage across the resistances connected to both inputs, and this voltage is interpreted by the opamp as signal, so it ill be amplified by the circuit gain (in your case gain is -10) and appear at the output. So the output will change. If the offset is large enough to clip the opamp then the output will be stuck near the positive or negative supply, and it will no longer operate in linear mode, which means the voltage between positive and negative inputs can no longer be considered negligible.

You can calculate this in your circuit by using an ideal opamp model, and add current sources in the inputs to model input bias and offset current. You can call them i- and i+, remember each input sinks or sources a slightly different current, the difference being the input offset current. Then calculate the voltage that appears, and you should be able to calculate what happens to the output.

bobflux
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    Nice answer... Only to note that newcommers hardly understand why input bias currents leave the base and pass through the input source. The usual notion of biasung is that it is made by an external circuit from the side of base (https://electronics.stackexchange.com/a/523072/61398). – Circuit fantasist Dec 26 '20 at 12:42
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In an ideal circuit you can't have nodes "floating" as that will result in infinite possible values for that node. This situation is called non-isolated system.

In a real scenario you can assume that a floating node is connected by a large resistance to some other node, typically ground. Now, you may need to consider other non-idealities like the leakage of the positive terminal of your OpAmp to be able to calculate the actual voltage that the positive terminal settles to.

Finally, it is worth mentioning that SPICE simulators will place a minimum conductance (1/resistance) to the global ground on every node (gmin). This is done precisely to avoid convergence issues caused by floating nodes.

In a CMOS OpAmp this resistance to ground will be smaller than the resistance modelling gate leakage of the transistor at the positiver terminal. Hence the positive terminal will be at 0V.

Alberto Gomez Saiz
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