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I have a couple of designs written in Verilog that I'm trying to synthesize with Synopsys DC Compiler. Specifically, I would like to maintain a 1ns upper bound on my critical path delay (CPD) on my designs — I have been able to successfully synthesize these designs with yosys (open source RTL synthesis tool) and meet this constraint.

I've tried setting a variety of parameters in a tcl script that I am using for synthesis of my Verilog modules, but none seem to be enforcing this upper bound on my CPD. Just to name a few things I have attempted: I've used the compile_ultra command, with and without the -retime flag (and the set_optimize_registers flag preceding this). I've tried using the set_max_delay command on all clocked paths, and any path from all inputs to all outputs. I've tried various settings of the clock period, to see whether increasing/decreasing the clock period from 1ns could help things.

Unfortunately, none of these has worked. Consistently, the DC compiler indicates that the timing slack has been violated and returns a CPD of nearly 4ns. I've been stuck on this issue for some time, and I'm not sure where else to turn to for help. I'm new to this tool, but I've tried reading through large portions of the DC Compiler manual in search of more parameters/commands that may help.

I would really appreciate it if someone had any advice on things that would enforce this 1ns constraint, or some intuition about the tool that could help. Thanks in advance.

Natasha A.
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    For tool specific questions, you will get better response in Synopsys forum or if you are student, use edaboard forum. – Mitu Raj Nov 30 '20 at 10:47
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    If you find it's taking much longer to compile with these constraints, and still failing, that possibly points to an irreducible worst path. Find that path from the timing reports, and re-pipeline it. (Repeat until constraints met). –  Nov 30 '20 at 13:04
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    @MituRaj thank you, I'll try those forums as well – Natasha A. Nov 30 '20 at 17:33
  • @BrianDrummond forgive me if this is a silly question, but I was under the impression that the `retime` flag would have re-pipelined the paths for me? Is this incorrect? I deliberately added a few extra, unused registers that could be moved around with retiming to set the pipeline stages. – Natasha A. Nov 30 '20 at 17:35
  • @NatashaA. That's certainly the stated intent of "retime" ... how well it works I couldn't say. I've never used Synopsys DC but my experience with other tools was not great. I tend to do my own retiming ... which works. –  Nov 30 '20 at 18:45
  • @BrianDrummond Ah, gotcha. I'll try that then, thanks! – Natasha A. Nov 30 '20 at 20:18

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