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I have come across material per review from my past encounters with digital sequential logic and I wanted to pose a specific and hopefully general question for the community to help shed some light.

I have found reference to the term "transparent" latch and I discovered that it permits the output to get the input to flow through the output of the latch.

However per my understanding I see that use of a latch (specifically "transparent") is discouraged in digital design, specifically sequential providing any sort of clock should not be used in this process.

What is the effective disadvantage of using a latch instead of a flip flop, and where are they effectively used?

Why is the left good, and the right is bad?

Diagram

Vahe
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  • Did you Google first? – DKNguyen Nov 27 '20 at 14:57
  • @DKNguyen, I will revise my question to indicate my current understanding, add details and hope not to branch into too many directions. Sometimes, switching between fields makes it difficult to assess the level of detail I need in my question – Vahe Nov 27 '20 at 14:59
  • We expect you to do some research and then ask a question that addresses *what you are having difficulty with*. A quick search reveals numerous excellent answers to this question. – Peter Smith Nov 27 '20 at 14:59
  • Let me revise now @PeterSmith – Vahe Nov 27 '20 at 15:00
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    Much better....... – DKNguyen Nov 27 '20 at 15:11
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    You should update the question title as well. – Finbarr Nov 27 '20 at 15:14
  • I forgot to specify 1T (single transistor isolated Gate MOSFET Drain/Source) as the element to serve as the transistor element to construct the 1 Bit clocked latch, whereby the gate is clocked and the drain/source are the data path – Vahe Nov 27 '20 at 15:50
  • [Why are inferred latches bad?](https://electronics.stackexchange.com/questions/38645/why-are-inferred-latches-bad) and [WHAT’S THE PROBLEM WITH LATCHES?](https://vhdlwhiz.com/why-latches-are-bad/) – maximus Nov 28 '20 at 11:36

2 Answers2

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To understand why an unclocked component of any kind is discouraged in sequential digital design you need to understand why a clock exists in the first place.

The clock keeps things in synch and makes it easier to design for. With no clock you have to rely on the delay between components matching up with each other so signals arrive at their next destinations neither too early nor too late (i.e. at exactly the right time). With thousands of branches and paths that are always changing, this is really difficult for very large circuits.

With a clock, everything just needs to arrive at its destination faster than the clock.

Since a transparent latch is not clocked, it is a bit of a renegade when using it amongst clocked components since it can allow signals to change when the clocked components are not expecting it. You can get away with it sometimes at the input or output of a system where things are more predictable, but in the middle of a system is often no good. It's about manageability of the timing. If part of the system is simple enough so you know what is going to happen, you can get away with it.

In FPGAs, specifically, transparent latches are discouraged because their timing is uncontrolled and FPGA architecture does not support them well so it produces unpredictable results.

Latches are a form of memory, be definition, and combinatorial circuits do not have memory by definition. But you can have simpler, unclocked, sequential circuits where the timing is more manageable. That's where transparent latches can be useful.

They are also useful to shield noise between circuits like ADCs, but that isn't digital logic design.

DKNguyen
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  • Please elaborate why the use of latch in this case is not encouraged, is there a specific disadvantage, and advantage in generic logic design? – Vahe Nov 27 '20 at 15:19
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    @Vahe Generic logic design doesn't have much meaning. – DKNguyen Nov 27 '20 at 15:24
  • Please substitute 'generic' with combinational – Vahe Nov 27 '20 at 15:24
  • Per your explanation of signal arrival time, does that imply path length needs to be short with delay elements in between to capture in a timely manner? – Vahe Nov 27 '20 at 15:28
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    @vahe In an clocked circuit, everything needs to arrive before the clock. Much faster doesn't matter as long as it is ready when the clock arrives. But in an unclocked circuit everything must arrive at EXACTLY the right time. Arrive too soon or too late and things break. – DKNguyen Nov 27 '20 at 15:32
  • So path lengths must be measurably and equally distributed to the from source to destination of a clock, what about the combinational path, does that need a tight control? – Vahe Nov 27 '20 at 15:34
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    Combinatorial circuits have no memory so have no latches. There is combinatorial (no memory) vs sequential (memory) and clocked vs unclocked. There are 4 possible combinations. It is not as much of a problem with combinatorial due to no memory, but if you have something big and feeding it really fast it can become a problem. – DKNguyen Nov 27 '20 at 15:36
  • "You can get away with it sometimes at the input or output of a system where things are more predictable, but in the middle of a system is often no good." Why is it disadvantageous not to put in middle but less to put at the boundary? "They are also useful to shield noise between circuits like ADCs, but that isn't digital logic design." Does the latch need to be configured like a Resistive Capacitive filter to achieve A/D conversion filtering? – Vahe Nov 27 '20 at 15:40
  • @vahe At input or output: It is about manageability. There is less going on there so you can more easily work around it. ADC: No. Imagine it like putting in earpugs when you know no one is talking to you so you can work in peace and only taking them out when someone is talking to you. Even if the ADC is ignoring, an SPI bus can be communicating to things other than the ADC and be disturbing it since they share a bus unless you disconnect the ADC from the bus,. – DKNguyen Nov 27 '20 at 15:42
  • Does this mean to disconnect entirely to not let external signal in OR just hold value like in the case of Sample/Hold? – Vahe Nov 27 '20 at 15:44
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    You just don't want the pins of the ADC wiggling when the comms are not to the ADC. There are multiple ways to fix the value at ADC pins during this time. Transparent latch is one. OR is another. – DKNguyen Nov 27 '20 at 15:45
  • I'll research this further, I am not able to visualize it in my mind. Please see my comment (last one) on question, I really forgot to specify a transistor as the Latch Element. Should I draw a picture? – Vahe Nov 27 '20 at 15:47
  • https://www.analog.com/en/analog-dialogue/articles/staying-well-grounded.html – DKNguyen Nov 27 '20 at 15:50
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In synchronous logic (particularly within FPGAs), the use of asynchronous parts (of which the transparent latch is but one) makes no sense, but there is a real use case for transparent latches even in a clocked system.

The venerable XX373 8 (and 16) bit transparent latch is a very common choice for address buffers in microprocessor based circuits, for example.

Many of those microprocessors also multiplex address and data; this is often the lower order part of the data bus but I have seen where the entire address / data paths are multiplexed - this saves physical pins and continues to this day for parallel interface memory subsystems.

We latch the address bus on an event known as ALE (Address Latch Enable) and the timing is often quite critical. This then maintains this address data for the remainder of the memory access cycle. The pins that were the address bus at the start of the cycle are now data bus bits.

See this page for a decent example.

Now consider a signal that will be gated by some external event and we do not know when that event will occur. This can be handled in synchronous logic but requires the use of 2 flip flops and a relatively fast clock (to synchronise the signal to the clock). A transparent latch is a good fit for this case where the clock rate may be slow compared to the event itself.

So neither is better or worse; it all depends on the use case.

Peter Smith
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  • Why is a transparent latch considered an asynchronous element? Does this extend to non transparent latch? – Vahe Nov 27 '20 at 16:17
  • A synchronous latch clocks data *through* on a clock. A transparent latch *freezes* data at the output when the enable is made false which may be a clocked signal but will not be the main clock itself. – Peter Smith Nov 27 '20 at 16:23
  • Is what you are describing clock gating? – Vahe Nov 27 '20 at 16:58