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Does the AXI specification impose any restrictions on the address space of slaves? I've read the latest version of the AXI specification (chapters A1-C2, ARM IHI 0022H) and could not find anything explicit. The most I could find was the following paragraph on section A3.4.1, "Address Structure":

A burst must not cross a 4KB address boundary.

  • Note :This prohibition prevents a burst from crossing a boundary between two slaves. It also limits the number of address increments that a slave must support.

This implies the address range for any given slave must itself not cross a 4KB boundary, but it's only an implication. If I'm reading the spec correctly, a slave is free to be assigned a 1-byte range or even a 2-byte range that crosses a 4KB boundary such as 0x0fff:0x1000, inclusive. Is this forbidden anywhere in the spec?

MuchToLearn
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1 Answers1

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Does the AXI specification impose any restrictions on the address space of slaves?

As per the standards, 4KB is the minm. addressing space for any slave on AXI bus interconnect. This is to simplify the address decoding in the interconnect. Of course it can have a larger addressing space, but again it has to be in the multiples of 4KB. The base addresses for slaves in the interconnect are also hence assigned in multiples of 4K.

Prohibition of a burst crossing 4KB boundaries is there in the standards to avoid the possibility of accessing a different slave during the burst.

a slave is free to be assigned a 1-byte range or even a 2-byte range that crosses a 4KB boundary such as 0x0fff:0x1000, inclusive. Is this forbidden anywhere in the spec?

A slave can't have that addressing range on the bus. Its base address has to be 4K aligned. Say, 0x0. Still 0xFFF, 0x1000 can be decoded as offset addresses by the slave, which correspond to the first and second registers of the slave. But that's an inefficient way of implementing a slave. Since the second memory-mapped register at 0x1000 crosses the 4KB boundary, the interconnect will now have to allocate an addressing space of 0x0 to 0x1FFF to the slave. That's a wastage of extra 4KB in the addressing space.

Also, you won't be able to perform a burst of two transfers on the registers at 0xFFF and 0x1000, as it crosses the 4K boundary, and hence violates the AXI standards.

Mitu Raj
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  • Thanks for your answer. Could you point to any place in the standard where this is asserted? - "As per the standards, 4KB is the minm. addressing space for any slave on AXI bus interconnect. " - "A slave can't have that addressing range on the bus. Its base address has to be 4K aligned." – MuchToLearn May 25 '21 at 00:12
  • It's not directly mentioned anywhere, but implied. I confirmed this behaviour of AXI interconnect while working with SoC designs on Xilinx Vivado FPGA Tool. Where a slave has to be assigned a pool of memory space in multiples of 4KB only, and base address with 4K aligned. Otherwise it's a design validation error. https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/8554/axi-4-burst-boundary – Mitu Raj May 25 '21 at 02:55