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I have a project where I am developing a basic processing core on a FPGA from logic gates. So of course I have an ALU that I am building out of logic gates. I have no issues with the rest of the ALU functions: add, sub, shift left/right, OR, CMP etc.

However I require to multiply two signed binary numbers using twos complement which may be negative or positive depending on previous calculations. Note I am using 32 bit architecture.

If the numbers were not negative I would have no problem as I could keep adding (e.g. A*B == A+A+A... B times) or using shift and add method. Also I don't care about processing speed as speed isn't a necessity in this project.

What is the best method for me to look at using when multiplying signed numbers?

David777
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    While this is conceptually messy, you don't really need to concern yourself with that as a practical matter. Have you examined the documentation for your FPGA's hardware multipliers? Typically they would support this, and typically you'd use those until you run out. Otherwise, your vendor-linked synthesis tool is likely willing to create one for you from logic fabric. Eg, you need to read the manuals for the target FPGA. DIY is definitely *not* the answer when you need an optimal solution in hardware but only in an academic setting where asked to prove you understand how it would work. – Chris Stratton Nov 25 '20 at 23:10
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    DIY is really going to be suboptimal when you have unused hardware multipliers which support this just sitting there. If you really wanted to, you'd first have to identify an algorithm, for example a naive one would be to convert to sign magnitude, or possibly do it wrong and then do a fixup of the offset afterwards. But that dodges the whole issue of how you are going to implement an efficient DIY *unsigned* multiplier anyway... – Chris Stratton Nov 25 '20 at 23:15
  • @ChrisStratton At the minute I am hoping to not use the device's hardware at all if I can help it. I know it is sub-optimal but this is in an academic setting, hence not using the FPGA's hardware at all. – David777 Nov 25 '20 at 23:16
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    So you're going to build a gate level multiplier. Um. OK. What have you learned from your own research on such so far? Or did you just want to be handed an inefficient answer here, rather than taking the efficient one already on offer from the chip vendor? If it's DIY, then you need to actually *do it* yourself, where "it" is at least the supporting research of the literature for a problem solved generations ago. – Chris Stratton Nov 25 '20 at 23:17
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    I don't understand what you mean when you say you are "developing...on a FPGA" and then say you are "not using the FPGA's hardware at all". Is this really just a homework question, and you are designing on paper? – Elliot Alderson Nov 25 '20 at 23:27
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    You want to research some of the basic gate level methods of doing a multiply operation. This is what designers had to do way back when when there weren't multiply-blocks that you could just drop into a design. – SteveSh Nov 26 '20 at 00:27
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    One way to deal with the signed inputs is to check the signs of the inputs, and based on them figure out the sign the result will have. Then do the actual multiplication on the absolute values of the inputs. Finally, if the result needs to be negative, negate the result. – Jerry Coffin Nov 26 '20 at 06:12

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