How is clock signal edge detection done / pros and cons of different approaches?

Question

I'm currently learning about flip-flops, and I'm curious about the different ways in which the clock signal is handled. So far I've come across 3 different techniques:

1. AND-ing the clock signal with the inverted clock signal (relying on the gate delay of the inverter to detect the rising edge of the signal).
2. Using a capacitor and a resistor to detect the rising edge
3. Using a MS configuration like this, which I've seen referred to as 'pulse triggered' instead of 'edge triggered', I guess because the clock has to go high and then low in order for the output to change.

I am wondering which of these approaches is typically used in practice, or if they're all used just in different situations? In the latter case I'd really appreciate an overview of when one might favour one approach over the other (and why). I'm sorry if this is very simple stuff, I tried a bunch of different searches before asking, but wasn't able to find anything that really answered my question.

Thanks!

Answer 1

Start with this datasheet of the SN7476/SN74LS6 flipflop

https://www.ti.com/lit/ds/symlink/sn54ls76a.pdf?ts=1606110683154&ref_url=https%253A%252F%252Fwww.google.com%252Furl%253Fsa%253Dt%2526rct%253Dj%2526q%253D%2526esrc%253Ds%2526source%253Dweb%2526cd%253D%2526ved%253D2ahUKEwju3ZnD_JftAhXWIDQIHcmQCaEQFjAAegQIAxAC%2526url%253Dhttps%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn54ls76a%2526usg%253DAOvVaw24Im-NlvUeTXtlodaWgNIA

and notice the "CLOCK" input has some transistors hanging off that pin.

You will notice similar input gate routing for the 74LS112 FF.

Realize the propagation delays of those "gates" may not be the same across all the gates. Thus some detective work is needed.