Logisim Help - Using Custom D Flip Flop

Question

I am trying to create a D Flip Flop to use in a bidirectional 4-bit shift register, using Logisim. However, when using my D flip flop the shift register acts just as a normal register setting the bit for all 4 D flip-flops outputs instead of one by one. It works properly when using the D flip-flop provided by Logisim but I am wondering how to achieve this using my own D Flip-Flop.

This is the design of my D Flip Flop

And this is the shift register (with the boxes representing the D Flip Flop)

Any help would be greatly appreciated

This is a latch, not a flip-flop. The output will keep following the input as long as the clock is high. A flip-flop will not do that. — user253751, Nov 18 '20 at 17:14
Unfortunately, there was no way to pass the clock output straight into the subcircuit so the latch was a workaround. — lilnut, Nov 18 '20 at 17:40

score 5 · Accepted Answer · answered Nov 18 '20 at 17:31

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D flip-flop provided by Logisim which you used for simulation was a positive edge-triggered D Flip-Flop. While what you have designed is a level-sensitive D latch.

You have to cascade two of those D latches in master-slave configuration to obtain a positive edge-triggered D Flip-Flop.

reference: Flip-Flops Wikipedia

answered Nov 18 '20 at 17:31

Mitu Raj

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Thank you for your reply – lilnut Nov 18 '20 at 17:33
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@lilnut This is the answer that you should select because it explains the why part. – a concerned citizen Nov 18 '20 at 21:10
For a rising-edge detector you can use the same configuration as the upper diagram, but put the not-gate on the other enable-pin. – Rd Basha Oct 25 '22 at 18:12

score 1 · Answer 2 · answered Nov 18 '20 at 16:35

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Shorten your clock pulse so that it is gone by the time the output data from one flip flop reaches the D input of the next. At the moment, with a long clock high time, when the new data arrives at a D input it is transferred straight through the flip flop and on to the next because the clock is still high.

This is a technique for producing a very short clock pulse, the duration of which is shorter than the time taken for the data to transition through the stage.

answered Nov 18 '20 at 16:35

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Unfortunately, even of you set the clock to `Ton` to 1 tick and `Toff` to 31 ticks, it still doesn't work. I suspect it calculates differently the states for the builtin D flip flop. – a concerned citizen Nov 18 '20 at 16:59
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@aconcernedcitizen yes, latches are different from flipflops. – user253751 Nov 18 '20 at 17:14
@user253751 True, but in real life you might get away with the inherent delays (also why you posted your answer). One of the reasons why I called it "concoction". – a concerned citizen Nov 18 '20 at 19:59

Logisim Help - Using Custom D Flip Flop

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