[Apologies in advance for possible misuse of terminology. I don't have any formal education in EE and am mostly self taught, so I may be lacking in some fundamentals.]
I am trying to design a discrete VCO (for modular synthesizer) using only transistors (2n3904/06 BJT and 2n5457 JFET) and passive components. The architecture is pretty typical for a synth VCO including expo converter, sawtooth core, and shapers for the other waveshapes. Frequency of the output waveforms is intended to cover lower range (1/1000 Hz - 20 Hz) and audible range (20 Hz - 50 kHz) enabling the VCO function as both an audio source and modulation source.
The issue that I am currently having is with the sawtooth core: the output waveform includes an unwanted DC offset by what appears to be some function of the charge current/frequency; at lower frequencies this offset is negligible but around 20 kHz it increases to as much as 500mV. In addition, the amplitude of the waveform seems to change (or the peak and trough are shifted by unequal amounts). The only effect on the signal as an audio source is a slight decrease in volume [with the offset contributing no perceivable change], however when used as a modulation source to vary the frequency of another 1v/oct oscillator the result is up to half an octave of unwanted pitch shift in the carrier waveform.
The LTspice simulation is not accurate to real life and even required several adjustments to cause oscillation, however it does demonstrate the offset issues. Offset of the waveform viewed from the node at the capacitor lead increases by about 70mV at the peak and 100mv at the trough when the frequency is swept from 10kHz to 20kHz. This signal is also amplified by the JFET input amplifier (I can't get this part of the circuit to work in LTspice), further increasing the offset at the final output.
JFET J1 is used as high impedance buffer, intended to buffer the voltage over the capacitor and nothing else; however it seems impossible to find a configuration that avoids creating a path for the charge current to enter as well. The same goes for J3. My guess is that a portion of the charge current enters the JFETs superimposing a DC offset on both the schmitt trigger input (base of Q1) and the final output signal (collector of Q7).
Any ideas on how to get rid of this offset and/or on what exactly is causing it?
One solution I have proposed is to mirror the charge current and subtract its voltage drop over a resistance from the buffered output at J1 and the final output as a sort of offset compensation. I have not had any luck with this approach, but perhaps I have implemented it incorrectly. Another solution is to AC couple the outputs, but I have not had any luck with this either.
I've spent about a week trying to resolve this with little success, so any help would be greatly appreciated. Thanks in advance.
Below are the .asc file contents:
Version 4
SHEET 1 1448 1128
WIRE 144 64 32 64
WIRE 32 144 -112 144
WIRE 176 144 32 144
WIRE 336 144 176 144
WIRE 112 224 32 224
WIRE 256 224 176 224
WIRE 336 224 336 144
WIRE -32 272 -160 272
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WIRE 256 272 256 224
WIRE 272 272 256 272
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WIRE 32 352 32 320
WIRE 336 400 304 400
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WIRE 752 432 576 432
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WIRE -16 512 -112 512
WIRE 512 512 -16 512
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WIRE 512 528 512 512
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FLAG 32 576 0
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FLAG 128 976 0
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WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 16 128 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 160 128 R0
SYMATTR InstName R2
SYMATTR Value 5k
SYMBOL npn -32 224 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
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SYMATTR InstName Q2
SYMATTR Value 2N3904
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SYMATTR InstName Q3
SYMATTR Value 2N3904
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SYMATTR InstName R3
SYMATTR Value 1.5k
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SYMATTR InstName R4
SYMATTR Value 530
SYMBOL res 320 384 R0
SYMATTR InstName R5
SYMATTR Value 1k
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WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
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SYMATTR Value -12
SYMBOL njf 256 608 M0
WINDOW 0 53 -51 Left 2
WINDOW 3 -21 -18 Left 2
SYMATTR InstName J2
SYMATTR Value J2N5457
SYMBOL cap 112 624 R0
SYMATTR InstName C1
SYMATTR Value 47n
SYMBOL njf 464 640 R0
WINDOW 3 54 50 Left 2
SYMATTR Value J2N5457
SYMATTR InstName J3
SYMBOL njf 704 640 M0
SYMATTR InstName J4
SYMATTR Value J2N5457
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SYMATTR InstName Q4
SYMATTR Value 2N3906
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SYMATTR InstName Q5
SYMATTR Value 2N3906
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WINDOW 3 32 56 VTop 2
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SYMATTR Value 100
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SYMATTR Value 15k
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SYMATTR Value 36k
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SYMATTR InstName R12
SYMATTR Value 50k
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SYMATTR InstName Q6
SYMATTR Value 2N3904
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SYMATTR Value 2N3904
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SYMATTR Value 1k
SYMBOL res 848 864 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
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SYMATTR Value 1.5k
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SYMATTR InstName R15
SYMATTR Value 10k
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SYMATTR InstName I1
SYMATTR Value PWL(0 500u 10 10m)
SYMBOL njf 80 656 M0
SYMATTR InstName J1
SYMATTR Value J2N5457
TEXT -160 1112 Left 2 !.tran 0 10s 0 0.0001s startup
I am using the following model for the 2n5457s:
.model J2N5457 NJF(Beta=1.125m Betatce=-.5 Rd=1 Rs=1 Lambda=2.3m Vto=-1.372 + Vtotc=-2.5m Is=181.3f Isr=1.747p N=1 Nr=2 Xti=3 Alpha=2.543u + Vk=152.2 Cgd=4p M=.3114 Pb=.5 Fc=.5 Cgs=4.627p Kf=10.45E-18 + Af=1)
