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i am designing this push and pull driver for external NMOS in my buck topology circuit.

i am well aware the gate charge ( based on Cgd) i need to turn FET ON and OFF at room temperature based on datasheet. But i do not know how much charge i need at 125 C in the design ?

all the spice models i have works only at room temp.

Gate Charge Q_GD = Slew Current x Rise Time or there are many other formulas. also data sheet shows how much minimum charge i need to turn on the FET

but my question is should i worried about gate charge at 125 C ? will it increases ? how to find it from datasheet?

AT hot RDS ON of the FET is increases , bigger RDSON more static power dissipation..but since i am switching the FET at 300 KHZ I am more interested in switching power dissipation.

My thinking is VGS of the FET will be hanging at 125 C so i think gate charge shold increases too.. how much that will be ?

Narendra Mane
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  • Get new spice models then is my advice because everyone I've seen, when used with the right simulation tool will adjust the model formulae to accomodate any temperature. – Andy aka Nov 14 '20 at 18:09
  • what i have seen is with spice model simulation, i see that gate charge is almost as high as three time compared to ita normal temp. value thats why i dont trust spice models at high temp. that doesnt make sense to me – Narendra Mane Nov 14 '20 at 18:42

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