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So we have AND, NOT, NAND, NOR, OR gates, but how are they created electronically/electrically?

For example, what makes NOT gate reverse the value?

placeholder
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user17534
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    Out of [transistors](http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/trangate.html). – Dean Jan 06 '13 at 17:34
  • [Here is a blog post](http://codefrieze.blogspot.co.uk/2016/06/making-boolean-logic-gates-from.html) I wrote that shows how to physically make the circuits from transistors and explains why they work. I found it easiest to understand after practically making then rather than just reading theory. The circuits are based on diagrams from [here](http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/trangate.html). – insano10 Jun 25 '16 at 17:13

5 Answers5

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I've turned this into a community wiki so we can collect cool logic gate implementations to which to refer to in the future.

To start with you have to understand transistors in a simple way. I will deal with CMOS since 99% of all logic that has ever existed (in number count) exists as CMOS.

There are two kinds of transistors used, PMOS and NMOS, here are their symbols: Fig 1

The transistors are electrically controlled current sources/sinks. The PMOS will source current (the dotted line in the diagram shows current flow when on) from a power supply (attached to source) through the drain and into other circuits when the Gate voltage is LOWER than the source. The NMOS will sink current into ground through the drain into the source (which in this case you should think of as a sink).

Please note that I've taken some liberties with naming for the sake of clarity.

PMOS is usually connected to a positive voltage and NMOS is usually connected to negative voltages typically ground.

Interestingly you can stack the devices to make various functions. Stacking two PMOS gives a current source that is controlled by two voltages, stacking two NMOS gives a current sink that is controlled by two voltages.

enter image description here

Notice that both Voltage at A (we'll call it A) and B BOTH have to be below +V for current to flow. Also notice that Both C and D have to be higher than Ground (that funny hatched triangle symbol) for current to be sinked (sunk ?). You could say "Both A AND B have to low for current to flow" and "Both C AND D have to be high for current to flow".

Just like you can "stack" (actually put in series), you can parallel devices. enter image description here

You could say that "either A OR B can be low for current to flow" for the PMOS and you could say that "either C OR D can be high for current to flow" for the NMOS circuit.

You will notice that already we are using logic language to describe function (AND, OR) so now we can start piecing together circuits.

First off the Invertor:

enter image description here

When Vin is at ground, the PMOS is turned on and can source current, but the NMOS is off and cannot sink current. As a result, the Vout pin tries to put charge onto any available capacitance and charges that capacitance up until it reaches the V+ level.

Likewise when the Vin is High, the NMOS is turned on and can sink current, but the PMOS is now off and cannot source current. as a result, the Vout pin tries to pull charge off of any available capacitance and discharges that capacitance until it reaches the Ground level.

A "high" on the input gives a "low" on the output, a "low" on the input gives a "high" on the output. It inverts!

If you look at the symbol for both the PMOS and the NMOS you'see that the gate looks like a capacitor on the symbol. This is deliberate as a MOS transistor IS a capacitor and it is mainly this capacitance that is charged and discharged during operation. Current is the flow of charge per time and capacitance is the storage of charge per voltage. Transistors turn gate voltage into controlled currents that then charge and discharge gate capacitances that turns that change in charge back into a change in voltage.

Now for the first two input gate the NAND gate:

enter image description here

The NMOS "stack" will only ever sink current under one condition, and that is when BOTH A & B are high. Notice that for that condition that BOTH the PMOS are off (i.e. do not source current). So in that condition Vout will sink current and the Vout will be Low.

In all other conditions at least one of the PMOS will be sourcing current and the NMOS stack will not be able to sink current. The output is then charged up and Vout = high.

A B Out
0 0 1
0 1 1
1 0 1
1 1 0

This truth table shows that if Not(A&B) AKA NAND. 0 = gnd, 1 = V+.

To turn into a AND gate you just need to invert the output.

enter image description here

And it's truth table:

A B Out
0 0 0
0 1 0
1 0 0
1 1 1

And next the NOR gate

enter image description here

I hope by now you should be able to get the truth table yourself.

C D Out
0 0 1
0 1 0
1 0 0
1 1 0

There is pleasing symmetry from NOR to NAND. the structure is a simple inversion.

Now the OR

enter image description here

and truth table

C D Out
0 0 0
0 1 1
1 0 1
1 1 1

Extending the designs to higher order inputs is easy, as shown by a 3 input NAND.

enter image description here

By placing NMOS and PMOS in series/parallel combinations you can implement various logic functions at a transistor level. This is often done for area efficiency, power efficiency or even for speed. These functions need not be strictly AND, OR or Xor functions. The following is known as as a AND/OR gate:

enter image description here

and has the following truth table.

C A B Out
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Least you think that this is the only way to implement these functions, I'll introduce a device that is called the transmission gate.

enter image description here

Both the NMOS and PMOS gates must be driven in opposition to work properly.

Here is a sample circuit of what you can do with an additional NMOS.

enter image description here

Here /A = Not(A) in digital logic

A+B = A OR B

A*B = A AND B

So you can see that only using 3 transistors you can implement A OR B. BE warned though that this circuit has serious side effects and is not generally used. But it is illustrative nevertheless.

here is a whole collection of TG based logic functions:

enter image description here

There is also Pass-Transistor-Logic or PTL. An example of such: PTL

KeyC0de
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placeholder
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    I wrote it myself because EE.SE is meant to be self contained and links are generally frowned upon. Additionally, I turned it into a community wiki so in the future cool ideas can be collected in here. – placeholder Jan 06 '13 at 20:20
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    Super answer!!! – wim Jan 07 '13 at 01:31
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    It's worthwhile to note that many situations require a function to NAND together the outputs of a few OR gates, or NOR together the outputs of a few NAND gates. An expression like `(A or B) nand (C or D)` may be implemented in a single level of logic using eight transistors--much more efficiently than using two full-fledged "or" gates and NAND'ing the result. – supercat Mar 15 '13 at 20:43
  • What are the 'serious side effects' of the TG OR implementation? – apalopohapa Nov 09 '13 at 19:56
  • @apalopohapa: The biggest side-effect is that TG logic circuits can sometimes back-drive their inputs, at least momentarily. I think the "/A" at the top of the "TG" or implementation should be "/B". Assume that's the case, and both A and B start out low. Initially, A and B will be connected to the output *and thus to each other*. If a rising edge on A occurs before a falling edge on /A, then current from A will be able to flow back out to B. Such back-flows, even if they are brief, can cause undesired circuit behaviors. – supercat Apr 22 '14 at 17:15
  • @supercat Thanks for the response. The circuit doesn't look right though, not even with the /B at the NMOS gate: When A=1, the bottom TG is off, so the only way to get a 1 at the output is through the NMOS. But the NMOS can only do so much to let 1s through. So it seems it should be a PMOS with /A at its gate. Regardless, I acknowledge the backdriving issues (thanks for the explanation). – apalopohapa Apr 22 '14 at 18:36
  • @apalopohapa: Hmm... maybe one could replace the top NFET with a PFET controlled by /A, though in that case the source of the PFET may as well connect to VDD rather than to A. – supercat Apr 22 '14 at 19:10
  • BTW, I designed a BJT-based XOR gate to control my dad's trailer's lights back around 1977 (left light = left blinker xor brake; right light = right blinker xor brake); it was conceptually a lit like the transmission-gate XOR which btw works better in NMOS than CMOS. – supercat Apr 22 '14 at 19:12
  • @apalopohapa fixed the NOR gate as I had the wrong polarity for /A input. /A is right. The cell can present a heavy load whereas a normal cell will only look capacitive. However, normal logic gates also have shoot through current (NMOS and PMOS drive conflict) so this is not unusual. What is true though is that you cannot cascade these devices (unless you can ensure that the low impedance drive ripples through) and they can be potentially slower as there is an additional channel length that is driven through. – placeholder Apr 22 '14 at 21:56
  • @placeholder Thanks. Just to clarify, we were talking about the OR gate that uses a TG plus a transistor. It seems that the NMOS should be a PMOS in order to let the full voltage of A=1 through. – apalopohapa Apr 22 '14 at 22:47
  • "The pass-transistor logic (PTL) is a better way to implement circuits designed for low power applications. The low power pass-transistor logic and its design analysis procedures were reported in [12, 13]. Its advantage is that one pass-transistor network (either pMOS or nMOS) is sufficient to implement the logic function, which results in lower number of transistors and smaller input load. Moreover, direct -to-ground paths, which may lead to short-circuit energy dissipation, are eliminated." https://www.hindawi.com/journals/vlsi/2012/173079/ – Brian Cannard Apr 14 '21 at 21:02
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check this link

http://www.instructables.com/id/Digital-Logic-Gates-Just-Using-Transistors/

NOT gate enter image description here

OR gate enter image description here

AND gate enter image description here

m salim
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  • An emitter follower will drop 0.7V just like a diode. The and and or gates should be followed by two inverters to amplify the voltage. – Oskar Skog Feb 19 '17 at 14:27
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The NOT gate in particular in CMOS consists of complementary PMOS and NMOS devices that are configured to invert the output.

Best advice I can give you is to look at the book Digital Integrated Circuits. It has everything you want to know about how to design logic at the transistor level.

Gustavo Litovsky
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Using RTL (Resistor-Transistor Logic).

Also, some gates are made by combining gates. For example, an XOR is an (OR) AND (NOT AND). Also, a NAND is just an inverted AND.

An inverter and a NOR: http://en.wikipedia.org/wiki/Resistor%E2%80%93transistor_logic
An OR is an inverted NOR.
An AND is a NOR with inverted inputs.
A NAND is an inverted AND.
An XOR is an OR ANDed with a NAND.
An NXOR is an inverted XOR, or an AND ORed with a NOR.

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You probably will understand it better if you have visual representation of what happen in logic gates. One of best place for this is this excellent interactive simulator falstad. It is java based and run from your browser.

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