I am trying to implement synchronous Serial protocol with SAME70 using board SAME70-XPLD. For that I need to generate clock of 2MHz. For that I am using TC module running at MCK/8 = 18.75MHz (MCK set to 150MHz), configured in compare mode. At each compare interrupt I update data and clock lines. I am not getting accurate timing results, Please suggest if bit banging with 2MHz clock is even possible or I am just wasting time?
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That processor has several hardware UARTs on it, why are you trying to implement one in software? – user4574 Nov 09 '20 at 05:46
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Which synchronous serial protocol and why not the available harware peripherals can't be used? – Justme Nov 09 '20 at 06:08
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@Sidk and what prevents using SPI for that? – Justme Nov 09 '20 at 07:25
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@Justme Bit stuffing and idle detection needs bit banging right? – Sidk Nov 09 '20 at 07:44
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@Sidk you already do bit stuffing encoding/decoding in software so what would be the difference? And idle state is just continuous frame delimiter transmission/reception? Anyway, software interrupts at 2 MHz is usually very suspicious. – Justme Nov 09 '20 at 08:46
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Presumably you could reconfigure when things turn around. If you need to respond to an external clock, that's all the more reason to use a synchronous serial engine. At some loss of efficiency, you could consider using DMA through a GPIO, but you'll probably end up with only one bit of meaning per byte (unless you treat the clock as sampled, too). – Chris Stratton Nov 09 '20 at 23:29