I referred this YouTube video for buck converter loop stability.
In the image we can see that the gain of the control loop we are talking about is Vout / Vin. Vout and Vin are both measured across the small value Rt resistor.
When we say that the gain of the op-amp decreases at the cross-over frequency, can someone please explain two things:
What will happen when the gain is decreased at the output of the op-amp with respect to the internal diagram mentioned in the above image?
What are we actually trying to simulate by increasing the frequency of the Vin at the input (bottom side of the Rt resistor)? In an actual buck converter working scenario, during very low load at the output of the converter the output voltage will decrease by some value. During light load, output voltage will not decrease. There will be no scenario in which there will be a load which will draw current at the frequency we are checking using a network analyzer. So, what real time converter scenario are we trying to simulate using this loop stability test using a network analyzer?
What factors determine the Vin input voltage from the network analyzer and the frequency of the input signal? I read that the frequency can be swept till some MHz and the amplitude of the signal show be in the 100-500mV range. Please explain why that is?