Nesting Elseif, If, Else in VHDL

Question

In the code below, I want to pull out statements surrounding the the ** asterisks ** below.

stateS0 = 1' and o_done = '1'

and

o_done = '1' and stateS0 = '0'

into separate comparisons using if or elseif.

I am struggling at how to pull out and compare if I am in state S0 and o_done = 1 and I am in state 1 and o_done = 1 into seperate if, then, else, elsif statements.

        process begin
        wait until rising_edge(clk);
        if (reset = '1') then
          stuff;
        else
          **if( StateS0 = '1' AND o_done = '1' ) then**
            stuff;
          elsif( ...stuff... ) then
            stuff;
          end if;
        end if;
      end process;
    
       
      process begin
        wait until rising_edge(clk);
        if (reset = '1') then
          o_done <= '0';
        else
          if ( ...stuff ...) then
            o_done <= '1';
          **elsif ( o_done = '1' AND StateS0 = '0' ) then**
            o_done <= '1';
          else
            o_done <= '0';
          end if;
        end if;
      end process;

I was thinking something like:

if stateS0=0 then if
o_done='1' then...

if o_done='1' then if
stateS0='1' then...

but can you do...

process begin
    wait until rising_edge(clk);
    if (reset = '1') then
      stuff;
    else
    if( state0 = '1') then
        if o_done='1' then
                stuff;
        end if;
    end if;
      elsif( stuff ) then
                stuff;
    end if;
  end process;

is that legal code ?

Or is this legal ?

  process begin
    wait until rising_edge(clk);
    if (reset = '1') then
      o_done <= '0';
    else
      if ( stuff ) then
        o_done <= '1';
      elsif ( o_done = '1') then
       if state0 = '0' ) then
        o_done <= '1';
      else
        o_done <= '0';
      end if;
    end if;
  end process;

But I am not sure about if I am nesting these right. Can you nest an:

if
if
end if
end if

within after an elsif or else ?

Can you nest elseif in if, then else statements ? Or elseif only check 0 or 1 conditions and not combinatorial conditions like if then else can ?

user4574 · Answer 1 · 2020-10-31T00:54:50.183

Can you nest elseif in if, then else statements ?

You are certainly allowed to nest "if" statements inside each-other. This is perfectly legal code.

if boolean_expression_1 then
    if boolean_expression_1a then
      --some statements
    elsif boolean_expression_1b then
      --some statements
    elsif boolean_expression_1c then
      --some statements
    else
      --some statements
    end if;
    --some statements
elsif boolean_expression_2 then
    if boolean_expression_2a then
      --some statements
    elsif boolean_expression_2b then
      --some statements
    else
      --some statements
    end if;
else boolean_expression_3 then
    --some statements
end if;

Or elseif only check 0 or 1 conditions and not combinatorial conditions like if then else can ?

The types of expressions you can put after "elsif" are exactly the same as for "if".

As for your code. if the type of o_done is a character type that has '1' and '0' as possible values, and State0 and State1 are both booleans then the following should compile without problems.

  if ( State1 ) then
    o_done <= '1';
  elsif (o_done = '1' AND State0 ) then
    o_done <= '1';
  else
    o_done <= '0';
  end if;

This is also legal

if state=s0 then 
    if o_done='1' then
      --some statements here
    end if;
end if;

if o_done='1' then
  if  stateS1='1' then
    --some statements here
  end if;
end if;

Nesting Elseif, If, Else in VHDL

1 Answers1