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I am studying about rail-to-rail opamp design and I am trying to recreate the Itail vs Vgs (in this case input common voltage) curve from the link bellow (pages 5 and 6): https://mixsignal.files.wordpress.com/2013/03/689-604rail2rail.pdf

I am having trouble to recreate the plot for the PMOS input stage. My VDD and VSS voltages are 1.8 and -1.8, and bias current is 30uA and the passive load is enough to keep the PMOS in saturation. I have a feeling I am missing something basic with how I instantiated the current generator...

schematic of pmos differential input stage

And here's my plot of the mosfet current vs input common voltage (you can see the drain current is a bit off, it looks as if I swept the Vds instead of gate voltage, and I didn't, I double checked):

pmos differential input plot of drain/source current vs input common voltage

And finally, I tried putting it all together in one schematic cellview but again, I think I am using the bias generators wrongly because now I can't seem to see the correct current in the NMOS branches even thought there's the current generator...

NMOS and PMOS input stages for rail-to-rail differential amplifier

I would appreciate some help. Thanks!

EDIT:

Taking a hint from the comments, I replaced the ideal current source with active current mirror source for both NMOS and PMOS differential input. I managed to get correct plots of drain current vs input common mode voltage and gm vs input common mode voltage but I still have troubles putting it all together into a rail-to-rail input stage (page 7 of the linked pdf).

Here are my tests: PMOS differential input with current mirror source

NMOS differential input with current mirror source

Rail-to-rail input stage with current mirror source

The MOSFETs in the current mirrors are all the same, and what bothers me is that the NMOS M3 is not referencing the correct current from the current generator. My bias current is 40uA, and in individual cellviews where I simulated the PMOS/NMOS differential inputs separately everything worked fine.

Putting it all together now I seem to be having an issue with the PMOS branch again. You can see the simulation results in the next picture.

Results showing error with PMOS input pair

From the looks of it it seems my PMOS pair is always on and with fixed current through them.

EDIT2:::

After close inspection I realized my input common mode voltage generator was not properly grounded but connected to VSS (-1.8V). It kept my PMOS gate voltage always sufficient to drive them in saturation.

After correcting that mistake I was finally able to have my basic simulation set up and running.

San
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  • Think about this: When both transistors are off what happens to the tail current? – dirac16 Oct 19 '20 at 21:06
  • Another hint: You have used an IDEAL current source, which means the current it supplies in no way changes. That means no matter what the gates voltage is the transistors will never turn off! – dirac16 Oct 19 '20 at 21:15
  • One more hint: Try to replace the current source with an NMOS transistor in a current mirror configuration, which is how we typically implement the tail current. – dirac16 Oct 19 '20 at 21:21
  • @dirac16 Thank you for the hints. By using the ideal current source I basically locked any activity of the mosfet, if they are off there's nowhere to sink the current from the ideal source. Just for testing, I added a parallel branch with the pmos pair containing one resistor, just to see if it would put something into motion, and it did... I implemented the differential inputs (both pmos and nmos) using pmos and nmos current mirrors instead. The results are edited into the Question Post. – San Oct 20 '20 at 12:48

1 Answers1

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The solution to the problem was not to use ideal current generator for biasing the input differential pairs since that would always keep the mosfet with fixed current.

Another problem that was described was an issue while simulating the whole setup for rail-to-rail simulation of the input stage (a PMOS and NMOS differential input branches).

The problem was in the voltage generator providing the input common voltage (ICM) that was not wired correctly. The negative terminal of the voltage generator was connected to VSS and not GND (as seen in the testbench picture in the Question Post).

For completeness I am posting the correct testbench with good simulation results. Enough to get anyone started for the rest of the discussion on rail-to-rail opamp design.

Corrected schematic of input differential pairs

Plot showing the correct current-voltage and gm relations

San
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