Problem with summer in VHDL

Question

I'm trying to do a summer in VHDL, but when I try simulate, appear an error. The code:

library IEEE;
use IEEE.Std_Logic_1164.all;
entity aritmetico is
port (A: in std_logic_vector(2 downto 0);
 B: in std_logic_vector(2 downto 0);
 Control: in std_logic_vector(1 downto 0);
 Out_hex: out std_logic_vector(6 downto 0);
 Out_bin: out std_logic_vector(3 downto 0)
 
 );
end aritmetico;

architecture circ of aritmetico is
 signal F,G,F1,F2,F3,F4: std_logic_vector(3 downto 0);
 
 component sum is
 port (A: in std_logic_vector(3 downto 0);
 B: in std_logic_vector(3 downto 0);
 F: out std_logic_vector(3 downto 0) );
 end component;
 
 component decoder is
 port (C: in std_logic_vector(3 downto 0);
 F: out std_logic_vector(6 downto 0)
 );
 end component;
 component mux4_1 is
 port (F1,F2,F3,F4: in std_logic_vector(3 downto 0);
sel: in std_logic_vector(1 downto 0);
F: out std_logic_vector(3 downto 0)
);
end component;

begin
 F1<= ‘0’ & A; 
F2<= A & ‘0’; 
F3<= ‘0’& B; 
F4<= B & ‘0’;


sum: Sum port map(F1,F,G);
decod: decoder port map (G, Out_hex);
 multip: mux4_1 port map(F1,F2,F3,F4,Control,F);
G <= Out_bin;

 
 
end circ;

How can I solve this?

Welcome to the site. It's as straightforward as you reading what the error messages say and make the corrections they describe. Out of interest, how did you manage to produce the rest of the VHDL if you can't solve these errors - have you copied it from somewhere? Is this homework of some kind? Just curious. Again, welcome. — TonyM, Oct 10 '20 at 14:36
This appears to have been copied out of a book or document where typesetting may convert apostrophes to non ISO 8897-1 characters, In this case lines 35-38 have character literals '0' using UTF-8 characters for left and right apostrophes instead of the ASCII/ISO 8897-1 equivalents. Fixing those leads to a label `sum` where the name is already used in a component declaration. Fix that and an error reading an out mode port `Out_bin` which should perhaps be mode in (there are no assignments locally). — , Oct 10 '20 at 20:02
@TonyM thank you! Yes, It is a homework, I'm starting to learn the VHDL and I'm trying to understand what the errors meaning. — Lucas Raphael, Oct 11 '20 at 00:07
Thank you for the awnser, The problem was that, and another problems I could solve it. About the better VHDL compiler, Can I compile my code in this website? How can I do that? I'm sorry for this question, but if you would have a link with a tutorial r something like this, I would be grateful! — Lucas Raphael, Oct 11 '20 at 00:22

score 6 · Answer 1 · 2020-10-11T11:14:39.497

You can find and fix the syntax errors. They are usually quite simple.

In this case, you may need a better VHDL compiler to help you diagnose them ...
ghdl ( https://github.com/ghdl/ghdl documented at https://ghdl.readthedocs.io/en/latest/) reports

ghdl -a aritmetico.vhd
aritmetico.vhd:35:8:error: invalid use of UTF8 character for '

presumably at F1<= ‘0’ which should be F1<= '0'

This sort of thing happens quite often if you copy/paste code from the PDF version of a textbook, and can be quite difficult to spot. Some type setter, unaware of the strict nature of VHDL syntax, decides to make the text look pretty...

There appear to be other errors too, but all in good time...

Problem with summer in VHDL

1 Answers1