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Spent a day trying to understand the maximum and minimum output voltage of the basic circuits as shown in this figureenter image description here

The problem is that I have come across different expressions for the output voltage for these circuits. My analysis:

Comparing only the high side voltages, or maximum voltage swings in both cases

The circuit on the left: Common source configuration, supposed to have a "rail to rail" swing, which according to me means that the output voltage swings from vdd to ground. Some literatures disagree. Me too. The maximum output voltage for PMOS to remain in saturation is \$ Vdd-Vo>=Vsg - |Vtp| \$ and hence \$ Vo=<Vdd-Vsg + |Vtp| \$. This is not rail to rail. Solving it further, \$ Vo=<Vdd-(Vdd-Vi) + |Vtp| \$ and hence \$ Vo=<Vi + |Vtp| \$. What does this even mean?

The circuit on the right: Source follower configuration, gain is one. The maximum output voltage for NMOS to remain in saturation is \$ Vdd-Vo>=Vgs - Vtn \$ and hence \$ Vo=<Vdd-Vgs+Vtn \$. The same expression as above!!

What am I doing wrong here?

EDIT: The circuit to the left, if Vo is rail to rail then the PMOS will enter triode region and current sourcing ability will drop drastically, so again how is it rail to rail!

RAN
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  • For the source follower, the maximum output voltage is Vin_max - Vgs and notice that if your Vin can reach Vdd then Vout_max= Vdd - Vgs. And for a Common source output stage, the output voltage can reach Vdd for a light load. See the real-world example https://electronics.stackexchange.com/questions/432775/op-amp-rail-to-rail-voltage-follower-latching-up/432924#432924 (TS922) – G36 Sep 22 '20 at 15:04
  • So for heavy loads the output voltage of common source will be Vo_max=Vdd-Vds_satpmos? i.e Vo_max= Vdd-(Vgs - Vtp)=Vdd+Vtp-Vgs. For source follower and considering heavy load, Vo_max=Vdd-Vgsn, so which one here will have a higher rail to rail swing, considering heavy loads? – RAN Sep 22 '20 at 15:15
  • In general, the common source output stage will have a higher rail to rail swing. But it hard to analyze the output voltage swing without knowing the driver stage. – G36 Sep 22 '20 at 15:21
  • Arent the circuits I posted are typical output driver stage? – RAN Sep 22 '20 at 15:29
  • Yes, But in your schematics, you drive these output stages from an ideal voltage source. Which is not the case in the real world. In this idealized scenario, the common source output stage will provide a higher output voltage swing. – G36 Sep 22 '20 at 15:35
  • But in the ideal scenario, for a heavy load, according to the derived equations the common source output stage does not prove to have a higher output swing than source follower... – RAN Sep 22 '20 at 15:37
  • Why not? I don't see it. – G36 Sep 22 '20 at 15:38
  • Let us [continue this discussion in chat](https://chat.stackexchange.com/rooms/113293/discussion-between-ran-and-g36). – RAN Sep 22 '20 at 15:39

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