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DDR2 RAMs have these control signals

RAS, CAS - address strobes

UDQ, LDQ - byte strobes

WE - write enable

UDM, LDM - write mask

Why do we need UDM and LDM? Can't you write a byte by asserting WE and only one DQ?

Here's a link to a typical data sheet. It tells me what the write mask does, but not why I need it. https://www.alliancememory.com/wp-content/uploads/pdf/ddr2/AS4C32M16D2A-25BAN_rev1.5.pdf

Mark Sullivan
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The UDQS/LDQS strobe signals are strictly for timing; they are not optional, and they must make a transition for every byte transferred and cannot be gated. Remember, data is transferred on BOTH edges of these strobes. The reason there is one for each lane is to relax the constraints on PCB trace skew to just a byte at a time, rather than across all of the bits of a wide interface.

The UDM/LDM signals are mask signals whose timing is the same as the data itself — indeed, these signals are themselves clocked by UDQS/LDQS just like the data is.

When doing a burst transfer where only some of the bytes are being written, it wouldn't work to omit some of the UDQS/LDQS transitions on only some of the bytes.

Dave Tweed
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  • I read Dave's answer a couple of more times and I think I understand. What you're saying is that it's not allowed to strobe only one of UDQS or LDQS. Therefore, to write just one byte, you need the mask bit. The fact that there are two strobes is nothing to do with the two bytes of the RAM word. There are two strobes, as Dave explained, for a different reason. – Mark Sullivan Sep 28 '20 at 14:17
  • The whole point of DDR memory is that you never transmit just one word at a time, you always transfer a "burst" of words. The xDQS signals are strictly for timing the burst, and have nothing to do with which bytes get written. That's what the xDM signals are for. – Dave Tweed Sep 28 '20 at 14:17
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    To be honest, I'm not sure why xDM is considered an important feature. In my experience, applications for DDR memory always have a cache (for random access) or buffers (for streaming access) closely associated with the DDR memory, and as a result, it is never necessary to mask individual byte writes. I'd love to hear of an application that actually requires the write mask. – Dave Tweed Sep 28 '20 at 14:26
  • Let me get clarification on one point. If I write two bytes at once, sending one transition on both UDQS and LDQS but I only have UDM asserted, do I write one byte of the addressed word and the other 8 bits is ignored? Or am I writing one upper byte to each of two consecutive words? – Mark Sullivan Sep 28 '20 at 14:34
  • UDM is a DDR signal, just like the data lines -- it is sampled on every edge of UDQS. You write an upper byte on each word for which it is asserted. – Dave Tweed Sep 28 '20 at 17:37
  • @DaveTweed, if I write a single byte to a location that isn't yet cached, I get an incomplete cache line, and having a DQM allows me to write that out to DDR memory without performing a read first, saving me 8 cycles and at least one bus turnaround. Pathological case would be `static char buffer[1024]; for(int i = 0; i < sizeof buffer; i += 64) buffer[i] = 0;`. – Simon Richter Jun 24 '22 at 04:01