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I'm using a STM32F746 running at 200MHz. A timer (tim2) is counting up at 100MHz and triggers an update interrupt with the following simplified ISR that writes a pattern to GPIOB

void __attribute__((section(".itcm_text"))) TIM2_IRQHandler(){
    
    GPIOB->ODR=pattern[index];
    
    index += 4;
    
    if (index >= size)
        index = 0;
    
    htim2.Instance->SR &= ~0x1; //clear interrupt flag
}

To improve speed:

  1. ISR in ITCM
  2. Data in DTCM
  3. Interrupt priority is 0 ( no other interrupts at that level)

When triggering on the rising edge of a GPIO pin, there is visible jitter on the falling edge. The time step is exactly 5ns (one clock cycle) and 25ns total.

Question: Why? Can it be improved without using the timers capture/compare output mode?

Usually the interrupt latency is depending on flash memory timing, but this shouldn't involve the flash memory at all. Could it be AHB bus connection between CPU and GPIOB(also running at 200MHz)?

enter image description here

techenthu
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  • If there are other interrupts happening or the bus has a transaction like read or write to another peripheral going on, it will delay the write that happens in the ISR. You could trigger a DMA transfer event instead of the interrupt so the DMA controller can at least shave some uncertainty out of the equation. – Justme Sep 11 '20 at 12:38
  • Without knowing anything about the MCU used: Have all instructions the same number of clocks to execute? If not, that explains the jitter, because the edge can happen any time, but the ISR may only be called "between" completed instructions. – the busybee Sep 12 '20 at 08:30

0 Answers0