2

I have a situation where I have Analog and digital grounds. In the picture below the white traces are AGND and the Green DGND. The grounds split where the external supply contacts the board.

I am trying to reduce inductance in these traces so as to keep the analog and digital sections as clean (noise-wise) as possible. What I have done is make every ground trace have its own separate trace so as to avoid any ground loops and everything connecting at its own STAR ground. Is this a viable way of keeping the circuit clean noise-wise?

enter image description here

Jirhska
  • 519
  • 3
  • 10
  • Here is a useful answer on using planes https://electronics.stackexchange.com/questions/306862/should-i-really-divide-the-ground-plane-into-analog-and-digital-parts/306896#306896 – analogsystemsrf Sep 10 '20 at 02:46
  • analogsystemsrf has given one link where relevent data is available.you didn't mentioned digital section what content is present/frequency of operation and in analog section what are the contents. This kind of approach you will have lot of inductance in GND which degrade the digital section. Have 2 planes for each GND and connect them at single point where noise is minimum. – user19579 Sep 11 '20 at 04:32
  • Let's say there are signals up to 100kHz somewhere on the board. I have bipolar supplies and grounds present throughout the board. AGND and DGND are somewhat sectioned off save for 4 DGND pins in AGND territory. Separating AGND and DGND on seperate planes is going to cause the power supplies to pick up a similar inductance because they will not have planes of their own. If I did a six layer board of digital analog sections (inner: VEE,VDD,GND) split I.e (AGND and DGND on one plane) I would still have to route a couple of connections like in the orginal photo as some pins are in another area. – Jirhska Sep 11 '20 at 12:03

2 Answers2

1

That's kind of a weird approach there, star earthing is useful for some sensitive traces on precision analog circuitry, but your approach has a lot of (self and mutual) inductance in the long legs which isn't helpful.

The best approach is to use the bottom layer as a near solid sheet of copper (actually a cross hatched pattern is better for manufacturing purposes). If the bottom ground plane gets split, e.g. so you can run power traces through it, then put bridges across it on the top layer.

You need to be careful where you put the "Agnd" node, this is essentially the centre of your star, if you keep all the high current power devices to the left of this point, and all the sensitive analog devices to the right, then you generally won't have a problem.

Here is a typical ground plane layout around an ATMEGA cpu , Agnd is circled in green, analog inputs are on the right side of this chip, pwm outputs go from the bottom of the chip, over to the MOSFETs on the far left (off screesn). Note the near complete ground mesh, and the low inductance coupling to it under the chip.

CPU trackwork

Here's an example of a top layer bridge to lower inductance, there is an analog multiplexor on right edge of picture.

ground bridge

BobT
  • 624
  • 3
  • 8
  • The star Earthing however eliminates shared resistance between nodes. If every trace in the "spider web" connections are decoupled with 0.1uF caps at termination, is the long traces that bad? Furthermore lets say they were not ground nets and were power nets such as AVDD and DVDD. Would the inductance matter? – Jirhska Sep 10 '20 at 00:34
  • 1
    @JoshuaGirgis true, star earthing eliminates shared DC voltage drops, However putting high current tracks on one edge of your PCB and sensitive analog tracks on the other edge reduces the sharing and reduces thermal EMF's, and enables a mesh earth to be used to lower inductance. The voltage drops on power tracks with 1oz copper carrying several amps of current can be large enough to use as low accuracy current shunts, I have some PCB's with a 1" long section of 100mil track to sense battery / motor current, (I don't that anymore, I have a more elegant Rdson sensor) – BobT Sep 10 '20 at 01:01
  • 1
    @JoshuaGirgis re the 100n decoupling caps, I don't think any of your power traces are close enough to gnd to get 100n coupling caps in. As for inductance analogues, imagine you are building a pine workbench from short lengths of 1" pine planks on a concrete floor, one end of the bench hardly moves when you hammer a nail in the other end.. Compare to making a piece of furniture made from cane, try hammering on it anywhere, and the whole thing will flop around., It is true lifting one end of the bench lifts everything at that end, but your cane structure is just flopping in the wind. – BobT Sep 10 '20 at 01:14
  • Sounds like the long traces are causing some issues with decoupling too. Let's say nothing is pulling more than 60mA. In fact way less and 60mA is an outlier. The PCB is for a sensor so every Analog trace is very sensitive. A Split ground plane is still going to have shared DC voltage drops and I can't imagine all the signals would play nice together if all the 'white' traces were meshed copper poured. To complicate things let's say there are bipolar supplies, AVEE, AVDD, DVEE, DVDD, AGND, DGND nets. Would opting for a 6 layer board be a better option? (ignoring price jumps) – Jirhska Sep 10 '20 at 13:19
  • 1
    Using a six layer PCB is like building a six lane freeway from your driveway to your garage- you only drive one car at a time. There is no such thing as "absolute potential" only potential difference, so you have to pick one datum point and measure from there, Agnd is usually this datum point. As all potentials are measured referrred to this node, it doesn't matter what the other power rails are doing. I've been designing sensitive analog electronics for 4decades, and have yet to use a 4 layer PCB, you can get to the Johnson noise limit and thermal limits of performance with two layer PCB's. – BobT Sep 10 '20 at 22:49
  • 1
    MY colleagues and I have worked on systems detecting signals at levels of 1 part in a billion of background. Multilayer boards can be a real headache prototyping as you can't get to the inside layers. If you desperately feel the urge to use a 4 layer PCB then make the two inner layers a solid sheet,. .Agnd for layer2 and Dgnd on layer 3 . Put almost all your power nets on the bottom layer, and all analog nets on the top layer. Having said that you will still get better results with a two layer board with proper partitioning of noisy & sensitive parts, than random layouts on multilayer boards – BobT Sep 10 '20 at 22:55
  • I think I understand now. Alas my design has over 300 components on it so it is almost impossible to route with a 2-4 layer board. I am probably going to split the ground plane into DGND and AGND and Keep the other internal layers for split power planes of VEE and VDD. Yet there are situations where on the 6 layer board I have DGND pins in the middle of AGND territory that need special routing from one copper pour to the middle of another to get to that pin. I have eliminated most star earthing this way save for maybe twelve of these outliers. https://imgur.com/a/bqqvfho – Jirhska Sep 11 '20 at 11:41
  • Ignore the last picture, which was a lone DVEE in AVEE territory on the VEE plane. https://imgur.com/a/Bv7vVTZ DGND is the copper pour on the Left of the picture and AGND is the copper pour on the right. The blue traces are an extra internal layer used to help route pins. The white traces are the outlier DGND pins in AGND territory. There are only 4 of them. Compared to about a 100 AGND pins that are no longer star earthed. As you can see I had to do this a couple times for Digital Power and ground. I don't think there is another way to get all nets to converge with all the power nets – Jirhska Sep 11 '20 at 11:54
  • I am thinking about doing a split ground plane because I really only have one mixed signal device.Thank you for all your help so far BTW @BobT. – Jirhska Sep 11 '20 at 11:55
1

The resistance between two points on a sheet of 1oz copper is 0.5milliohms per square, so the resistance is 0.5mR no matter how far apart the two points are, (but slightly higher near the edge, hence the 5mm blob where your star point comes together looks like a network or resistors (see below) , leading off from these are your thin tracks, each of aspect ratio 100:1 so R=50mR. The tracks are 1" long so about 10nH long, so a total of 20nH between two nodes, and 10nH of mutual inductance.

If you connect to a ground plane instead, then you get the same mesh of resistors at the blob , but the blob fills the whole board. And all the stray resistors and inductors disappear.

schematic

simulate this circuit – Schematic created using CircuitLab

See also https://www.edn.com/total-inductance-in-the-return-path-rule-of-thumb-7/

and https://www.edn.com/sheet-resistance-of-copper-foil-rule-of-thumb-13/

and https://www.edn.com/resistance-of-a-copper-trace-rule-of-thumb-14/

Note that both resistance and inductance of a 2D rectangle (or 3d rectangular block) scale according to the ratio of length to width (for a given thickness) the actual length is irrelevant, so the lowest resistance and inductance occurs with a squarish sheet, i.e. the entire layer on the PCB.

To prevent the PCB from buckling as it passes through solder ovens/baths you make the solid layer as a mesh (so little bits of copper have space to expand into).

BobT
  • 624
  • 3
  • 8