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I have a few questions about what this code does and how it works:

x <= '{default:'1} ;
  1. What is the purpose of the "default" keyword ?
  2. What is the purpose of the inner single quote apostrophe before the 1 in this case ?
  3. What is the purpose of the inner single quote apostrophe before the { in this case ?
shaiko
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    [Stackoverflow](https://stackoverflow.com/questions/22697639/what-should-default1-do-in-system-verilog) has a question on this. –  Sep 09 '20 at 19:59
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    I've read the question on Stackoverflow before posting this one. I'm not asking the same thing. – shaiko Sep 09 '20 at 22:40

2 Answers2

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The inner single quote before the 1 is a numeric literal fill. The '0, '1, 'z, and 'x literals will be extended to fill the width of whatever context they are used in.

The outer single quote before the { means that this is an assignment pattern to an array or struct. Assignment patterns require a value for every element of the array or struct, which can be positionally ordered or matched by name/index. When matched by name/index, the default: serves as a match to any unspecified element.

This is all explained in section 10.9 Assignment patterns in the IEEE 1800-2017 SystemVerilog LRM

dave_59
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  • In fact your answer states the same as mine, except you use more formal terms. But it's in no way more correct. – schnedan Sep 10 '20 at 07:14
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As far as I know:

  • its SystemVerilog
  • '{} defines a (unnamed) struct
  • default:'1 , as the default width is 32bit, is 32x '1' as constant

(if not correct, please correct me)

schnedan
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    This is completely incorrect (other that yes, this is SystemVerilog as it was so tagged) – dave_59 Sep 09 '20 at 21:45
  • dave_59, so what's the correct answer ? – shaiko Sep 09 '20 at 22:05
  • @shaiko I already answered. https://stackoverflow.com/help/someone-answers – dave_59 Sep 09 '20 at 23:58
  • @schnedan - Since we don't know what `x` is, we don't know what it defines. And there is no default width for `'1` in this context. We need to know `x`'s width. – dave_59 Sep 23 '20 at 08:23
  • @dave_59 https://electronics.stackexchange.com/questions/179142/systemverilog-structure-initialization-with-default-1 http://www.testbench.in/SV_03_LITERALS.html https://stackoverflow.com/questions/22697639/what-should-default1-do-in-system-verilog ... seems I am right, you not. – schnedan Sep 23 '20 at 08:36