2

I try to use TCXO (KT7050A24576KAW33TAD) at 24.576 MHz through frequency multiplier (PLL) x4 (NB3N511DG) to clock the I2S bus (SAI domain) at 98.304 MHz on a MCU (STM32L4R5VIT6). Signals are not what I expected. Can someone help me to understand what I miss ?

1 - SCHEMATIC

TCXO and multiplier schematic
(I remove R15)

2 - IMPLEMENTATION

TCXO and multiplier implementation

3 - TCXO OUTPUT SIGNAL

TCXO signal
Take on pin 5 of KT7050A24576KAW33TAD probe x1 with short ground spring

I expect a "CMOS" signal from KT7050A24576KAW33TAD but it look like more than "Clipped Sine Wave". Page 77 of the Kyocera Catalog I expect the following signal

KT7050A24576KAW33TAD CMOS output

4 - PLL/MULTIPLIER OUTPUT SIGNAL

Multiplier output signal
Take on pin 5 of NB3N511DG probe x1 with short ground spring

I use CubeMX for quick test, I think STM32 pin "CLK_SAI" is well put in alternate function as "SAI Ext Clock". I expect a "CMOS" signal too on NB3N511DG output (square with lower min and higher max). (CLK_S0 and CLK_S1 are pulled low from the STM32)

5 - LACK OF UNDERSTANDING THE DATASHEET

When i bought the TCXO I see it's a CMOS output from supplier :
KT7050A24576KAW33TAD supplier

But friend of mine caught my attention on KT7050A24576KAW33TAD datasheet and suggest it can be use in both mode :
KT7050A24576KAW33TAD datasheet

But I don't understand how to change mode from "Clipped Sine Wav" to "CMOS" mode...

This is the first time I play with TCXO and multiplier, I probably don't understand something (or more), can someone help me to find my issue ?

EDIT 1 : MEASUREMENT PROBE

I use 1x probe with short ground spring like this :

probe x1

EDIT 2 : NEW MEASUREMENT PROBE x10
Many BIG THANKS to Justme and Tom Carpenter

Ok, with x10 probe (set on probe and oscilloscope) i got :

Output of TCXO :
TCXO output with x10 probe
It's look like a CMOS signal :)

Output of PLL :
PLL output with x10 probe
This is a sinwave :( I

So the input of PLL seem good now, but the output is not what I expected. The NB3N511DG datasheet say :

Phase−Locked−Loop (PLL)design techniques are used to produce a low jitter, TTL level clockoutput up to 200 MHz with a 50% duty cycle.

TTL/CMOS Output with 25 mA TTL Level Drive

The logic diagram show a TTL/CMOS output buffer

Datasheet PLL diagram

And caracheteristics tell me :

Datasheet PLL caracteristics

Does CMOS not implied square signal ?
Can someone help me to understand why I don't get a almost square signal at NB3N511DG PLL output ?

EDIT 3 : NEW MEASUREMENT PROBE x10 @50MHz
Many BIG THANKS to Justme

Pff... Don't forget Shannon-Niquist theorem... Don't try to look at 100MHz signal width 100Mhz bandwidth oscilloscop...

So I change the PLL multiplication coefficient to x2 to go lower than FS/2.
I can go to 49,152 MHz, here is the measurement :

PLL signal @49,152 MHz

It's look like what I expected !

rom1nux
  • 498
  • 3
  • 18
  • Are you using 1x or 10x probes? Are you using a long ground clip or short ground spring? – Justme Sep 07 '20 at 08:44
  • @Justme I use a 1x probe with short ground spring (I edit the post to put picture of the probe) – rom1nux Sep 07 '20 at 08:55
  • Looks like a bandly compensated probe – Tom Carpenter Sep 07 '20 at 09:37
  • @Justme well, I understand I don't know how to do measurement :(, thanks for you help sir – rom1nux Sep 07 '20 at 10:42
  • @TomCarpenter many thanks to you too sir, Sadly I need to learn about measurement ... – rom1nux Sep 07 '20 at 10:43
  • @rom1nux That is a whole another problem. Your oscilloscope has a 100 MHz bandwidth. It cannot show a 100 MHz square wave. – Justme Sep 07 '20 at 10:53
  • How my bad, Niquist basis... thanks – rom1nux Sep 07 '20 at 11:21
  • You've received answers which explain how this is on the surface a probing/measurement problem, but the actual signal integrity may not be without issue, either. Ideally in a case like this you'd use an *internal* PLL (your chip has one reserved for each audio domain) and never have that 98 MHz square wave run externally at all. It's not even clear that your chip can even accept an external master clock *input* specifically for the I2S - how are you routing this into the chip? And for that matter, why do you want to overclock it? – Chris Stratton Sep 07 '20 at 13:25
  • @ChrisStratton I need a really clean clock for sensor acquisition, the internal PLL coefficients of this STM32 don't allow me to set the exact I2S/TDM clock I need even if I change the HSE frequency (!i create scipt to test all combinations, I go other constraints on other clock domain). So that why I use the the external SAI clock.It's not overclocked, it's common frequency for FS clock on TDM bus. – rom1nux Sep 07 '20 at 20:58
  • Of course you can get this exact clock frequency if you feed a factor of it into the internal PLL. But you didn't answer the question about what pin you are trying to feed this 98 MHz signal into. – Chris Stratton Sep 07 '20 at 21:00
  • @ChrisStratton No, You cannot set 98.304 MHz from PLLSAI1 or PLLSAI2 without changing HSE,(not all factor are available and there is constraint on the inner stages of theses PLL) If you change HSE you change other clock domain (CLK48, CORE, SDMMC, etc...) and you cannot (CLK48 is not really tolerant) or I dont want to lower my core or my SDMMC bus. Believie me there is no combinations available for my specifications. Almost all STM32 allow to clock the I2S/TDM peripheral with external clock. Take look on datasheet page 17 on diagram "EXTCLK" on SAIx block, or page 83 "SAI1_EXTCLK" – rom1nux Sep 07 '20 at 21:20
  • Exactly, you change the HSE, and then you adjust clk48 back to the closest possible. Are you using something such as USB which would prevent that? What's unfortunate is that while you seem to have a dedicated external clock input, you don't have one to feed the SAI PLL. Bringing in the ~98 MHz signal may well cause you board design issues which a 25 MHz one would not, and you don't have and probably can't afford an instrument to meaningfully probe those. Do the best signal integrity design job you can and hope for the best, I guess. – Chris Stratton Sep 07 '20 at 21:25
  • @ChrisStratton Yes I use USB, and don't want to degrade other clock domain. Yes I do my best for board design, I will quickly see if my samples are well acquired or not... – rom1nux Sep 07 '20 at 21:35

2 Answers2

7

The problem is the 1x probe mode. It does not have enough bandwidth in 1x mode.

Set it to 10x for more bandwidth.

Always use 10x probes, unless you know you must use 1x mode, and that does not happen very often.

Justme
  • 127,425
  • 3
  • 97
  • 261
  • I add new measurement with x10 probe, and hum... well...this work really better...I just don't understand why I got sinewave instead of square signal at PLL output now... Many thanks to take time to help me sir. – rom1nux Sep 07 '20 at 10:46
5

Other answer is spot on regarding the first problem.

The scope says "100MHz" just above the screen.

That means it doesn't have enough bandwidth to show the third, fifth. 7th etc harmonics of the 98MHz output signal : these are necessary to represent a square wave.

Therefore it can only display the fundamental. So it will appear as approximately a sinewave, with no further hint about its actual waveform.

After Edit 3 : the third harmonic of 50MHz is 150MHz : well outside the scope's nominal bandwidth. So it's greatly attenuated, leaving a rather sad excuse for a square wave.

Note that the Nyquist frequency is 500 MHz, since the scope samples at 1 GS/s. However the analog electronics (including teh anti-aliasing filter) limit the bandwidth to much less than this : it's probably 3dB down at 100 MHz (to claim 100 MHz BW), and 10dB or more at 150 MHz.

You are now getting as close as you can expect with the tools you are using.