This device has 8 drain channels, shared source, and a single shared gate:
How is this different from tying all the drains together and using a single FET?
I suppose you could have different drain voltages, but what might be a real-world application?
The manufacturer says it is useful in "smart phones" and as a "load switch". The lack of any matching specifications would tend to indicate it's intended for switching only.
Maybe a low-side switch for loads connected to multiple supply rails.
I don’t have an updated design in mind, but the problem with fast switching parallel FET is the Miller capacitance can vary with Vgs(th) e.g. 2~4V and when the loads switch the current sharing can result in overheating or worse shoot thru with a complementary driver and insufficient deadtime.
However when within the same chip, they tend to be very well matched. These chips are also 1ns fall time and 1.2ns rise time at test load, you may consider them for level shifted complementary drivers for Pch, Nch in half bridges that use <1A with almost no shoot-thru deadband with carefully selected output stages. Layout and load skew must be properly design to achieve this in a >1MHz SMPS .
Then use the 3rd for logical level feedback.
or use any combination of the 3 for driving fast loads with nominal 1/4 ohm resistance each.
if you ever get a requirement to clamp multiple bus loads on the low side to 0V in 1ns , these would do the job, for some odd reason.
You might consider these for multi voltage boost flyback generators with low power different voltage zener loads.
