I am a student and trying to understand the MOS transistor.
So I have simulated the transfer curve of a MOS in Cadence and done a parametric sweep for WL (500n, 1000n).
Here you can see the plot sqrt of the transfer curve Vgs/Id. (Level 1 Model)
If I change to a level 49 model in Cadence the curve is no longer quadratic. There are two effects I can see in the plot. First the curve rises exponentially/quadratic around the threshhold voltage and then it flattens out. Why is this so?
The exponential behavior is known as subthreshold conduction and is seen when the MOSFET's channel is in weak inversion. In this mode of operation, diffusion current dominates (while in strong inversion, the device operation is best explained with drift current).
From an analog design standpoint, operating in this weak inversion regime allows for highly power-efficient design. In particular, \$g_m / I_D\$ (one particular figure of merit used in some designs) is quite good, as is the output impedance of the MOSFET. This allows for high gains to be realized with low current consumption.
With wide transistors operating in this weak inversion scheme, it is also possible to achieve good gain-bandwidth products under the assumption that output capacitive loading contributes the dominant pole (since the frequency of that pole is roughly modeled by \$G_m / (2\pi C_L)\$. This assumption is often valid when doing VLSI design.
The tradeoff is the speed of the transistor itself, as \$f_t\$ is relatively poor in this mode of operation. Once the input signal reaches a frequency of \$f_t\$, the transistor can no longer perform any meaningful amplification: to get 1 nA of sinusoidal small-signal current through the drain, the gate capacitance must be driven with that same amount of current to actually modulate the channel. This creates issues for higher-frequency signals, since the high transconductance achievable with wide transistors begins to interact with the capacitances inherent to the transistor itself.
While I don't have exact numbers from any particular CMOS process which I am allowed to share, I can show this approximate chart that adequately conveys the rough behavior of these two figures of merit as the inversion coefficient changes.
Notice that as the transistor's channel is driven into weaker and weaker saturation, the transconductance efficiency tops out at some value, while the transit frequency drops further and further, into values as low as the kHz range in extreme situations.
In the processes that I worked with (mostly older mixed-signal CMOS, sub-micron but not anywhere near FinFET sizes), the typical values for gm/Id (transcondutance efficiency) are in the 20s to 30s in weak inversion. This comes from the fact that the weak inversion drain current in a MOSFET is like that of a BJT, but with a non-ideality factor \$n\$:
$$\begin{align} I_{bjt} &= I_0 e^{\frac{V_\pi}{V_t}}\\ I_{fet} &= I_0 e^{\frac{V_\pi}{n V_t}} \,\,\text{(for weak inversion only)} \end{align}$$
With some mathematical rearrangement, it can be shown that the transconductance efficiency in each case is \$\frac{1}{V_t}\$ and \$\frac{1}{nV_t}\$, respectively.
Ft can be over 10 GHz even in an older (larger than 100 nm) process.
The conductance exponential becomes linear when the current becomes limited by the bulk resistance from size and characteristic of the junction geometry.
This Vg/Vt ratio is sufficiently the RdsOn resistance dominates the linear value. Although the term saturated is opposite for technical reasons. .
RdsOn is rated at Vgs=>2 to >=2.5x Vt {or Vgs(th)} or some std. voltage like 5, 10 etc., where the bulk resistance of a FET dominates Ron and is linear, almost.
Yet Vt has a wide tolerance unlike Vbe. The std. old ones are 2~4V =Vt while the newer ones are <<1V
For BJT’s the supersaturated transistors are just superhigh hFE so when Ic/Ib=50 or less, and hFE is 500 to 2000 ($) so its a good switch with lower capacitance than FETs with Rce=Vol/Ic as the saturated bulk resistance which is pretty linear except for thermal effects. So instead of the usual Ic/Ib=10 for Vce=Vce(sat) the better ones are 20 to 50. This is tends to be around <10% of the best case linear hFE.
Remember that when the quadratic Ron vs Vgs goes less than the bulk series resistance, RdsOn is usually constant enough with power design margin so linear power dissipation except that in most cases RdsOn increases with temperature so it loses linearity.
FWIW, the term quadratic describes something that pertains to squares. So when in doubt replace the word quadratic with exponential.
The SPICE level 1 model implements the simple FET theoretical (quadratic) characteristic. However this simplified model ignores some real-world effects in a FET
Around the threshold voltage, the device conducts a small current that is exponentially dependent on the gate voltage. Thus, even for VGS < VTH, it will conduct (slightly). As VGS exceeds VTH, this weak inversion current 'dies out', and the simplified quadratically-dependent current flows.
At larger currents (VGS >> VTH), the effects of source series resistance (internal to the FET) become noticeable, reducing the effective VGS that the channel sees, and making the current become lower than the square law values.
Drain resistance can also become a contributor. This reduces the internal VDS of the FET, and because of either output impedance, or exiting saturation, the current will be lower than expected.
