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Logic buffer is usually depicted like this:

Standard logic buffer

But can this work equally well? Simplified logic buffer

And if it's not the case, why not?

Martin
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    Because FETs aren't switches in source follower configuration. –  Aug 14 '20 at 12:59
  • The FETs look symmetrical with this symbol, but they are actually not. – user253751 Aug 14 '20 at 13:40
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    @user253751: Actually, they are symmetrical. But that doesn't address the fact that with the NMOS, in order to conduct, the gate voltage needs to be significantly higher than at least one of the other two terminals (lower with the PMOS). The second circuit doesn't meet this requirement. – Dave Tweed Aug 14 '20 at 13:59
  • @Martin, In my answer below, I roughly revealed the philosophy of the two circuit solutions. It would be good, if something is not clear to you (and it probably is), to let me know. I will be happy to explain it to you... – Circuit fantasist Aug 15 '20 at 14:57

5 Answers5

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What we need

As a rule, the authors of circuit textbooks willingly show us how circuits are made... and how to calculate them. But they frequently forget to tell us why they are made this way; so usually we have to find the explanation ourselves.

The challenge

It is a big challenge to reveal the "philosophy" behind these legendary complementary stages... to find the answer to the question, "Why are they made exactly this way?".. and to the more specific question here, "Why not a source follower?" I will try to do it in a human friendly manner, without any special terms and definitions that impede the intuitive understanding at this initial stage.

The OP's idea

It really makes sense. He simply asks, "Why do we need to make a follower by two cascaded CMOS inverters (4 transistors in total) when such a simpler circuit (CMOS follower of only 2 transistors) exists?"

Really, it exists... and it is widely used in analog amplifiers... but here we are talking about digital circuits (logic gates). Let's consider what is the difference between them.

Follower vs inverter

Following vs amplification. The output voltage of the CMOS follower is a copy of the input voltage. So, if the input signal has poor (sloping) transitions, the output signal will also be poor.

In contrast, the CMOS inverter has significant gain during the switching because each of the transistors acts as a "dynamic load" to the other. As a result, the input signal is amplified and its transitions become steep. So the CMOS inverter improves the input signal.

The fact that logic gates are amplifiers makes it possible to build latches by introducing a positive feedback (simply by connecting the output of the cascaded inverters to the input). It is impossible to make this by the source follower because its gain is less than one.

Output voltage drops. Analog circuits work in the middle range of the power supply (in active mode); their output voltage does not reach supply rails (ground and VDD). So, the voltage drops across the drain-source parts of both transistors can be significant... and they can be connected in a CMOS source follower configuration.

In contrast, digital circuits work close to supply rails; their output voltage is either 0 V (ground) or VDD (+5 V). This means that the voltage drops across the drain-source parts of both transistors should be almost zero... and they should be connected in a CMOS inverter configuration. So, the CMOS inverter provides voltage levels almost equal to the supply rails.

Input voltage thresholds. The voltage follower needs small voltage thresholds of the transistors since they determine the difference between the input and output voltage (i.e., here the voltage threshold is something undesired). That is why, BJT are more suitable for this configuration since their base-emitter voltage VBE (0.7 V) is a relatively small threshold.

In contrast, the complementary inverter needs significant voltage thresholds (but still < VDD/2) since both transistors switch close to middle (i.e., here the voltage threshold is desired). So, this topology can not be implemented by BJT because of their small thresholds. MOS FETs are more suitable for the inverting configuration because of their high gate-source voltage threshold Vth.

Biasing. Another problem of the follower is the absence of biasing. As a result, in a region of 2Vth, both transistors ate cut-off and the output is "floating". There is no such a problem in the invertor where at least one transistor is on.

Versatility. Cascaded inverters have another (great) advantage vs the follower - there is another input (output). It is used in RS latches and RAM cells.

Circuit fantasist
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  • Please, do not remove the introductory part of the answer. It is written with the idea of showing a deeper meaning of things than a specific circuit explanation. We are different and do not need to be unified; SE would only lose from this... – Circuit fantasist Aug 15 '20 at 14:50
  • So using source follower is not only of no benefit, but it makes the signal's amplitude even lower, therefore the edges will be even less steep than before the follower, as it's gain is less than one. On the other hand, the gain of a single inverter is far more than one, thus it makes the amplitude higher and/or edges steeper, therefore it enhances the signal. Do I understand it correctly? – Martin Aug 15 '20 at 18:45
  • @Martin, That is right... This circuit was created for the purposes of analog circuitry and we should not ask it to work as a digital circuit. To be quite precise, there are actually no digital circuits; they are analog circuits forced to act as digital. The inverter is also an analog circuit but it functions as such (in active mode) only in a very narrow area in the middle. – Circuit fantasist Aug 15 '20 at 20:07
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    Thank you very much! – Martin Aug 15 '20 at 20:51
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No, your proposed buffer will not work well. MOSFETs are not ideal switches. For example, to make an NMOS conduct well you must bring its gate voltage significantly above the source voltage. In other words, when the transistor is conducting the source voltage must be significantly less than the gate voltage. In your buffer, if you bring the NMOS gate to Vdd the NMOS source (your output) will be significantly less than Vdd.

The "significantly less" value is determined by the threshold voltage of the transistors.

Elliot Alderson
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  • Which electrodes are sources and which ones are drains (second image)? – Martin Aug 14 '20 at 13:38
  • @Martin, The drains are connected to the supply rails and the sources are joined; so a complementary source follower is built. – Circuit fantasist Aug 14 '20 at 18:05
  • Thank you very much. – Martin Aug 14 '20 at 18:31
  • @Martin For a MOSFET in general, the notion of "source" and "drain" is determined by the relative voltage of these nodes at any instant in time. For NMOS, the node with the lower voltage acts as a source. For a PMOS, the node with the higher voltage acts as the source. – Elliot Alderson Aug 15 '20 at 16:38
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EECS 151/251A - Spring 2020 - Digital Design and Integrated Circuits - Lecture 9: CMOS

On the slide about transmission gates (#50), it is written that

  • nmos should be used to pass zeros and
  • pmos should be used to pass ones

Which I find a beautifully simple rule of thumb (I don’t know if it’s always correct though…)

Greenonline
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The original schematic shows two cascaded CMOS inverters. The outputs are taken from the common-drain node.

In your schematic, the drain is tied to ground and the output is taken from the common-source node. As Elliot has detailed in his answer, your buffer gate will not work.

A two-transistor buffer is nothing different than a push-pull (a.k.a. totem pole) output:

schematic

simulate this circuit – Schematic created using CircuitLab

Maybe you should also ask another question like why two inverters instead of a single push-pull buffer?

Rohat Kılıç
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  • Rohan means it will work for analog signals >Vgs outside Vdd,Vss but not inside with gain using logic levels , so it is not a valid solution. All transistor switches are inverters.. Two complementary make it low impedance bilevel inverter. FETs work better as they crossconduction with low current due to RdsOn > 300 Ohms. So CD4xxx series can be used up to 18V while 74HC cannot be used more than5.5V due to ~ 50Ohm RdsOn and 74ACTxx~ 25 Ohm. So for TTL the inverts use both NPN drivers with high side as emitter follower strong<2V and Weak up 4V – Tony Stewart EE75 Aug 14 '20 at 12:43
  • @Tony Stewart Sunnyskyguy EE75, Maybe, it would be interesting to note that the "low impedance" of the inverter is different from the "low impedance" of the follower - the first is "ohmic low impedance" while the second is "differential low impedance". The inverter has extremely low impedance only at the two steady states (0 V and VDD) while the follower always (because of the negative feedback). TTL output stage uses an n-p-n top transistor since it is better tnan p-n-p... and it is controlled by an additional transistor. In CMOS this happens by itself without additional means. – Circuit fantasist Aug 15 '20 at 17:43
  • @Circuitfantasist an OA uses NFB but logic never does so the impedance is always low and cross conducting somewhat higher RdsON but still low Z = Vol/IOL while the TTL uses CC for high and CE for Low on each NPN but the drive is current limited and asymmetric, so low Z on “0” and higher V and Z on “1” yet balanced noise immunity in the defined limits for worst case voltage. – Tony Stewart EE75 Aug 15 '20 at 17:49
  • @Tony, How ugly this TTL output stage is... and how beautiful and symmetrical the CMOS stage is... – Circuit fantasist Aug 15 '20 at 18:27
  • I though it was clever how they changed from 74 to 74S , 74L all compatible with a threshold of 1.35V – Tony Stewart EE75 Aug 16 '20 at 07:24
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FET diagrams like those shown for logic are a simplification. The bubble/no-bubble notation is shorthand for a p-FET or n-FET. It’s not really showing inversion per se, although that’s what the pair of FETs do when their sources are connected to VDD and Vss, as is usual for CMOS.

Looking deeper, a FET configured as a switch requires the right gate-source voltage to turn on properly:

  • p-FET: source connected to VDD, gate is lower than (VDD - threshold)
  • n-FET: source connected to Vss, gate is higher than (Vss + threshold)

For CMOS logic then, p-FETs are normally used on the pull-up side, while n-FETs are used in the pull-down.

On the other hand, the ‘flipped’ orientation doesn’t work. You won’t get the desired non-inverting behavior, as the gate-source biases are wrong.

Related: Why are the voltages the way they are in this transistor circuit?

Why do we use an inverter at the end in CMOS AND and OR gates?

Transmission gate logic bends this source-to-VDD/Vss rule some, but nonetheless still requires correct gate-source biases to pass a signal.

hacktastical
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  • That said, I think analysis of what Vgs is, is far more useful than other answer "it doesn't work because it isn't an emitter follower". However, you followed suit by explaining the thing that works, and not saying much of anything about the proposed circuit. Going through the steps of "NMOS Vgs is Vg - Vs, which in the proposed circuit is Va - Vy. PMOS is Vs - Vg, which in the proposed is Vy - Va. Under the assumption that Vy = Va, both Vgs voltages are zero, both transistors are turned off, Vy floats -- and **this doesn't depend on the input voltage Va**" I feel would fill in OP's gaps – Ben Voigt Apr 24 '23 at 19:10
  • This is one of those evergreen questions. See the linked answers which dive into this more. – hacktastical Apr 24 '23 at 19:23