I was reading through the documentation of the AXI standard when I came across the interconnection matrix shown below. In short, the interconnection matrix provides a path for several masters to connect to several slaves at the same time. If there was only 1 master, then the interconnection matrix is basically a demultiplexer. However, with many masters, it is much more powerful. I was wondering how we can design such a thing in VHDL.
The AXI Interconnect Matrix is an example of a cross point switch, also known as a crossbar (pg 11 of the AXI IP documentation explicitly calls it that).
Below is a block diagram of a simple one I designed for a project I am working on:
In this example we have two entities that can read/write from one of 3 blocks of RAM. From L-R, the inputs (arbitrarily chosen as data and control signals can flow either way) are fed to 2 demuxes while they outputs are fed by 3 muxes. Control of what connections are actually used is governed by a separate Control Logic block.
The actual VHDL for this is rather simple. You just need to design a a Mux (if or case statement), a Demux (same as mux) and some control logic. By using generate statements to select the number of muxes/demuxes required you make a quite elegant structure that is fantastically scaleable.
