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The $dist_erlang function in Verilog-2005 takes an argument called mean. Some information about the mean argument of $dist_erlang is found in this paragraph from section 17.9.2 of the spec:

enter image description here

They also provide C code for how simulators ought to internally implement $dist_erlang (from page 320 of the spec). This code implements a formula that can be found on Wikipedia for sampling an Erlang distribution.

erlangian(seed, k, mean)
long *seed, k, mean;
{
    double x, log(), a, b;
    long i;
    x = 1.0;
    for(i = 1; i <= k; i++)
    {
        x = x * uniform(seed, 0, 1);
    }
    a = (double)mean;
    b = (double)k;
    x = -a * log(x)/b;
    return(x);
}

I'm no expert on statistics, but I'm pretty sure that the multiplication by mean / a at the very end of this function is not gonna result in a distribution whose mean is mean. This would imply that every Erlang distribution sampled from using the equation on Wikipedia has a mean of 1, which definitely isn't true.

Am I missing something here, or is this an honest to goodness error in the Verilog spec?

John M
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    This question may get better answers on math.SE instead of here. I'm not familiar with the Erlang distribution, at least. – Hearth Jul 16 '20 at 17:37
  • Thanks for the advice! Anyways, after staring at it for another 10 minutes, I found my error, so I'm going to delete this question. – John M Jul 16 '20 at 17:40
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    Before you do that, consider a self-answer. It may be useful to others. – Hearth Jul 16 '20 at 17:40
  • BTW the Verilog-2005 LRM is obsolete. Please use the [IEEE 1800-2017 SystemVerilog LRM](https://ieeexplore.ieee.org/document/8299595). This is now section 20.15.2 – dave_59 Jul 16 '20 at 17:57
  • AFAIK, the tools I'm using (yosys) don't support SystemVerilog. That's why I'm looking at the 2005 document. – John M Jul 16 '20 at 18:04
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    OK, but do check the latest spec for any corrections that might have been made, next time. – dave_59 Jul 16 '20 at 18:58

1 Answers1

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I was confused about this because I was confused by the parameter naming in the Verilog spec and I made a basic algebra error.

The mean can be given by k / lambda. The sampling formula requires 1 / lambda, which is the same as (k / lambda) / k.

Taking mean as an argument instead of lambda might have been considered more user friendly.

John M
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