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Working with:

  • Lattice XP2-30 or XP2-40
  • Tentatively a BGA484; almost certainly some BGA 1mm-pitch package
  • Synplify PRO, with SystemVerilog

Skill level: Beginner / early-intermediate.

If I have a custom design (that is, to be implemented in a custom-made board) where there are several outputs for which timing must be matched to within, say, ±1ns (or whatever specified amount, perhaps less than 1ns), how can I ensure that these constraints are met?

Because I'm designing the board layout, I do not have the option to measure the skew, and then compensate for it by applying the opposite skew by adjusting the traces lengths. Not only that: I assume that any change in the HDL / re-synthesis / re-map / re-placement can potentially change the skew.

Another detail that constrains / complicates the problem: I would like to map the IO pins such that the layout gets easier to accomplish; for example, if I have the external chip (the one on the right in the image below) where I need to connect pins 1 to 5 with tight skew constraints, then that would strongly encourage the choice of FPGA pin assignments such that 1↔A16, 2↔B16, 3↔C16, 4↔D16, and 5↔E16 (just an example, assuming that A16 to E16 are IO pins), to have straight(ish) and near-equal-length traces and avoid using vias or having to "detour" some traces making a round behind the other one, etc.:

enter image description here

How can I ensure that the tool will be able (or will attempt) to implement things such that with that pin assignment, the timings and skew requirements can work?

Cal-linux
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  • This sounds like a lot to ask. Explain why you need to constrain the timing so severely. – Elliot Alderson Jul 08 '20 at 21:22
  • @ElliotAlderson -- for example, if I were to implement a gigabit ethernet controller (maybe the skew requirements are not that tight between the controller and the PHY, and more like in the differential pairs from the PHY to the magnetics?); or DDR memory; IIRC, for DDR3 at 800MHz, you have to match the time-of-flight to within ±10ps or less. Even if I were told that such thing is just not feasible: how can I tell that it is not? I feel I should be able to ask the tool to attempt it, and then have the tool determine that it is not possible to meet the timing requirements. – Cal-linux Jul 08 '20 at 21:38
  • BTW: is ±1ns such a severe timing constraint? At 100MHz, that's 1/10th of the period, which seems a reasonable margin to impose to the skew. With these chips, it doesn't sound like a 100MHz output signal should be unthinkable — tough and tricky to pull off, yes, but it should be feasible, no? – Cal-linux Jul 08 '20 at 21:41
  • I agree, if you keep traces short enough with respect to the wavelength then transmission line effects don't take hold. (But you still have something like an RLC filter, you can use saturn PCB tool to check parasitics. – Voltage Spike Jul 08 '20 at 22:26
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    If you use the output registers in the FPGA output cells and clock them from the same internal FPGA clock from one of the PLLs, you will minimize the skew between your outputs, especially if all of the registers are in the same I/O bank. It is difficult to control skew between combinatorial logic outputs unless you basically hand place the logic cells in the design by using placement constraints. – crj11 Jul 09 '20 at 01:11
  • Remember that you said "perhaps less than 1ns". Since you haven't specified a lower bound it's pretty hard to give you a good answer. If you turn around and say you want 100ps matching that's 1% of the period, and you will need to carefully control how signals are created **and routed** on the FPGA. – Elliot Alderson Jul 09 '20 at 22:06
  • Well, but in principle it should not matter what the limit I have in mind is; I was hoping that there would be some way to instruct the tool about these limits; then the tool (knowing all little details about the internals of the circuits) will attempt to meet those requirements, or report that it could not. I could then choose to specify that I want a skew below half a femtosecond..... and that would be my problem, if I'm willing to waste time waiting for the tool to surely tell me _unable to comply_. – Cal-linux Jul 09 '20 at 22:17

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