Subtracter with VHDL

Question

I have this:

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.std_logic_arith.all; 

ENTITY FullSubtracter1 is port(In1, In2: in std_logic_vector(31 downto 0);
                           Overflow: in std_logic_vector(0 downto 0);
                           Diff: out std_logic_vector(31 downto 0));
end FullSubtracter1;

ARCHITECTURE FullSubtracter1_1 of FullSubtracter1 is
signal tmpDiff: std_logic_vector(32 downto 0);
signal tmpOverflow: std_logic_vector(0 downto 0);

BEGIN
   tmpDiff <= std_logic_vector(conv_signed(to_integer(signed(In1)) 
                        - to_integer(signed(In2)), Diff'length), Diff'length);
                    
   Diff <= tmpDiff;
   tmpOverflow <= '1' WHEN (In1(15)=In2(15) AND tmpDiff(15)/=In1(15)) or
                        (In1(15)/=In2(15) AND tmpDiff(15)/=In1(15)) ELSE '0';
   Overflow <= tmpOverflow;
END FullSubtracter1_1;

And I get on this line of code:

tmpDiff <= std_logic_vector(conv_signed(to_integer(signed(In1)) 
                        - to_integer(signed(In2)), Diff'length), Diff'length);

The below messages:

Error: C:/Modeltech_pe_edu_10.4a/examples/Full_Subtracter1.vhd(16):(vcom-1078) Identifier "signed" is not directly visible and then this message:

Error: C:/Modeltech_pe_edu_10.4a/examples/Full_Subtracter1.vhd(16): (vcom-1394) Type conversion operand must be a single expression that is not a range.

Any suggestion?

You have "used" two incompatible definitions of "signed". That means, neither of them is visible. Get rid of std_logic_arith and the "conv_signed" function calls from it. Declare your ports and signals signed not std_logic_vector as far as the assignment permits, to eliminate useless type conversions. — , Jul 06 '20 at 12:22
If the comment by @BrianDrummond was helpful to you, you can ask him to post it as an answer and then you can upvote it. — P2000, Jul 06 '20 at 17:47
@p2000 I tend to throw the little ones back nowadays. If you feel it's worth converting to an answer, please be my guest. I spend too long here as it is. — , Jul 06 '20 at 17:50
Hahaha, sure. I saw that @konstantinosDms was new, so just wanted to make sure he knew he could give credit, if not here, then in other future posts. — P2000, Jul 06 '20 at 17:56

score 2 · Answer 1 · answered Jul 29 '20 at 07:49

You have "used" two incompatible definitions of "signed". That means, neither of them is visible. Get rid of std_logic_arith and the "conv_signed" function calls from it. Declare your ports and signals signed not std_logic_vector as far as the assignment permits, to eliminate useless type conversions.

-Brian Drummond

Subtracter with VHDL

1 Answers1