Synchronous reset within always block - BLOCKING vs NON-BLOCKING assignment

Question

I am trying to use synchronous reset within an always block for a Moore FSM. Following are 2 blocks of code implementing the same, one uses Non-Blocking assignment and other uses Blocking assignment.

always @(posedge clock, posedge reset) begin
 if(reset==1) 
     current_state <= Zero;
 else
     current_state <= next_state; 
end

vs

always @(posedge clock, posedge reset)
begin
 if(reset==1) 
     current_state = Zero;
 else
     current_state = next_state; 
end

What would be the difference in outputs between these 2 blocks of code?

Have a look here: https://electronics.stackexchange.com/questions/163018/asynchronous-reset-in-verilog — P2000, Jun 21 '20 at 05:29

Tom Carpenter · Accepted Answer · 2020-10-24T13:27:52.767

2

From a synthesis perspective, there will be no difference between the two pieces of code.

For simulation, in isolation, both pieces of code will have the same behaviour. However, if you start mixing blocking and non-blocking assignments for synchronous logic, this can sometimes cause weird/inaccurate simulation behaviour due to the way simulators convert the parallel logic into sequential operations.

The same applies to both synchronous and asynchronous reset cases.

edited Oct 24 '20 at 13:27

answered Jun 20 '20 at 17:32

Tom Carpenter

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Yeah i have edited the post, but synchronous or asynchronous, my question applies to both types. – Ashlesha Sunil Agate Jun 20 '20 at 17:53
@AshleshaSunilAgate The first part of my answer applies to both async and sync reset. – Tom Carpenter Jun 20 '20 at 18:00

Synchronous reset within always block - BLOCKING vs NON-BLOCKING assignment

1 Answers1