1

Is there any difference between 'high in vhdl and $high in verilog??

simran
  • 21
  • 1
  • Generally speaking, yes - both return the highest index possible. But maybe a more specific question would yield a more specific answer. – po.pe Jun 11 '20 at 11:47

1 Answers1

1

The difference is $high in Verilog can only return a integer type whereas the 'high attribute in VHDL returns the largest value in the type of the range.

dave_59
  • 7,557
  • 1
  • 14
  • 26