How to know if a verilog code is sequential or combinational?

Question

How to know if this piece of code is for a sequential or a combinational circuit?

Look for some 'always @ ()' documentation. [You may just find your answer](https://class.ece.uw.edu/371/peckol/doc/Always@.pdf). — Vicente Cunha, Jun 09 '20 at 11:21

score 6 · Accepted Answer · edited Jun 17 '20 at 16:34

6

This will synthesize to sequential logic. If b is 1, then output will become 01. Consider the case when both the inputs a and b are 0. No condition of your code is satisfied, which means that the output will be unchanged. This implies that we are storing previous value, for which a latch is required. This occurs due to incomplete if else statements, that is, all the cases are not covered.

edited Jun 17 '20 at 16:34

Shashank V M

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answered Jun 15 '20 at 04:20

user2488336

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score 0 · Answer 2 · answered Jun 13 '20 at 18:39

You can find out if a circuit is combinational if the circuit does not depend on previous states. Also a combinational circuit is time independent. In case that one of those conditions are not met, your circuit is sequential.

Regarding verilog code, one way to find out the combinational part from your module is to see the always block and its sensitivity list.

Always@ (*) block is used to describe combinational logic and logic gates. The star (*) represents the sensitivity list specifies which signals should trigger the elements inside the always@ block to be updated. Also a rule of thumb is to use only blocking assignments in an always@(*) block (e.g OUT = A & B).

Concerning your verilog code, there is a CLK signal in your sensitivity list and non-blocking assignments are used (which are used only in sequential logic circuits). However, I would say that your code is combinational because it is not synchronized with clk signal and the ouput is changed according to a or b inputs and the output does not depend on previous state (such as q <= ~q). In Verilog, if you want to create sequential logic use a clocked always block with nonblocking assignments. If you want to create combinational logic use an always block with blocking assignments

@panterhei , "Always@ (*) block is used to describe combinational logic and logic gates' - Even **latches** can be built using **always @(\*)** block. — Shashank V M, Jun 14 '20 at 12:41
Your first sentence is correct, but your final conclusion is wrong. Consider what happens in OP's code if both `a` and `b` are 0. — The Photon, Jun 15 '20 at 04:43

How to know if a verilog code is sequential or combinational?

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