Op-Amp Integrator's virtual ground

Question

I have been using op-amp TL072C in charge integrator configuration. R = 1k Ohms and C = 100 uF. Vin is a DC signal of 1 V. VCC = 10 V and VSS = -10 V.
I get the expected output which is VSS, when a DC signal given as input. But the strange thing is that virtual ground voltage increases to about 0.65 V after output reaches VSS. Attached the screen shot.

Why does the virtual ground voltage increases after output reaches to -VSS or saturation voltage ?

Probe 3: Input
Probe 1: Output
probe 2: Virtual Ground

Are you sure it was a TL072 op-amp? Is the question why it reaches 0.65 volts instead of 1 volt or is it about why it stops being a virtual ground? — Andy aka, Jun 06 '20 at 07:24
It is TL072. The question is why it stops being virtual ground after output is saturated. — Naveen Sajjanar, Jun 06 '20 at 07:40
It saves others time if you add a link to the datasheet what you are using. Think of it next time when you ask a chip related question. In some cases there are multiple vendors for the same main part number. Though in general they are identical, there might be nuances between their behaviour. — Horror Vacui, Jun 07 '20 at 11:59

score 8 · Accepted Answer · answered Jun 06 '20 at 07:45

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Is the question why it reaches 0.65 volts instead of 1 volt or is it about why it stops being a virtual ground?

The question is why it stops being virtual ground

An op-amp with negative feedback tries to maintain the inverting input at the same voltage as the non-inverting input by adjusting the output voltage so that the potentials are equalized. Once the op-amp output hits the end-stops, it no longer can continue to adjust the output in the correct direction to maintain a virtual earth.

answered Jun 06 '20 at 07:45

Andy aka

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Got it. Does it mean that if output didn't hit the rail (VSS ), virtual ground would be maintained at near 0V since non-inverting end is tied to ground ? Other question: Do you think that it should have reached 1 V instead of 0.65 V, why ? – Naveen Sajjanar Jun 06 '20 at 08:07
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Correct and it's easier to analyse in a pure op-amp amplifier circuit - just think of the op-amp as an error amplifier in a control loop - it tries to minimize the error just like any control system does (if that makes sense to you). It should reach the same voltage as the input because once the output hits a solid end stop, you can think of the capacitor as an open circuit but, maybe as Spehro said in his answer, the capacitor is a bit leaky or is an electrolytic with the wrong polarity across it. – Andy aka Jun 06 '20 at 08:09
Cool. I do have electrolytic capacitor there. I will flip it and check. – Naveen Sajjanar Jun 06 '20 at 08:20
@NaveenSajjanar You shouldn't really be using electrolytic capacitors in integrators because of this very problem. Flipping it may fix today's problem but it just means that when you input a different voltage the problem occurs again. – Andy aka Jun 06 '20 at 08:26
ok. I will keep that in mind. – Naveen Sajjanar Jun 06 '20 at 08:40
Electrolytic capacitors are not very good in one more sense - their capacity varies a lot (+100%, -50% or more) depending on temperature, age of the capacitor, voltage applied, phase of the moon, etc... not exactly the properties one wants in a precise analog circuit. Leakage current is high and also variable. – fraxinus Jun 06 '20 at 14:22
@fraxinus you should properly address that comment to the intended recipient in case anyone thinks it is an intended criticism of my answer. – Andy aka Jun 06 '20 at 14:26
@Andyaka It is not a criticism of your answer, but an addition to your comment. – fraxinus Jun 06 '20 at 14:46
@Andy aka, the capacitor is not an open circuit when the op-amp output voltage reaches the negative rail. It will continue charging but by the input voltage source. When its right plate stops "moving" down, its left plate (virtual ground) will start "moving" up. Actually, the input source and the op-amp output are connected in series and in the same direction so their voltages are summed. Thus they form a composed voltage source that drives the RC circuit. After the output voltage stops, the capacitor tries to reach (in an exponential manner) the total voltage of this composed voltage source. – Circuit fantasist Jun 07 '20 at 05:10

score 3 · Answer 2 · answered Jun 06 '20 at 08:56

If you have an ideal op-amp with infinite power supplies, the integrator output voltage would integrate to minus infinity as the capacitor needs to be charged with 1mA to keep the op-amp inverting terminal at 0V.

However you have a real world op-amp with limited supply voltage. As soon as the output voltage hits the output limit, it cannot go any more negative and it will stop pulling current via the capacitor so it cannot keep the inverting input at 0V.

score 2 · Answer 3 · answered Jun 06 '20 at 04:30

One would expect the voltage to increase to the input voltage, since there is no longer dv/dt to draw current from the resistor.

Since it is not, that implies either measurement error or a large leakage current through the capacitor (maybe an electrolytic capacitor with the wrong polarity).

horta · Answer 4 · 2020-06-06T23:21:57.277

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Here are your op-amp internals.
If you shut off (1) by raising it to Vcc+, then you pinch off (2) which pinches off the mirroring (3)s. You've effectively shut down half of your differential pair. With the right (3) pinched off, all of the current flowing down from the top current source feeding the differential pair (input jfets), the current now has nowhere to go in it's normal path when operating correctly.

Instead of that current going through (3)s, it has to go entirely through the gate of (4) to get to Vcc-.
Further, it has to either go through the resistor or go through (5)'s gate and then another resistor.
This means that you'll at least have a Vbe + resistance or Vbe + Vbe + resistance depending on the two resistor values at the bottom terminal of IN+'s jfet. Jfets are transistors which require ~0.7 volts to turn on. So you'll generally have the input floating at 0.7 above the prior semi-calculated number.

edited Jun 06 '20 at 23:21

answered Jun 06 '20 at 04:33

horta

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Thanks for the explanation. I partially understood your answer. Can you please draw the current direction when in normal operation and when node 1 is shut off ? It will make it more clear for me. Is this phenomenon only limited to JFET amplifiers ? – Naveen Sajjanar Jun 06 '20 at 08:03
@horta You would get more upvotes if you turned your wall of text into separate lines or paragraphs, making it much easier to read. Just a heads-up. – Jun 06 '20 at 22:49
The current of the tail current source can flow through C1 and Q5 to VCC-. A typo: bipolar transistors have bases, not gates. Thumbs up for adding the schematic from the datasheet! – Horror Vacui Jun 07 '20 at 11:56

score 1 · Answer 5 · answered Jun 07 '20 at 09:06

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If the output Voltage reached the vss. The capacitor C is nearly cut off. So the feedback branch / C doesn't work. The invert input voltage can be What you input. It is no longer VIRTUAL Grounded. Caution, too high voltage may destroy the op amplifier. For more details, See the Data sheet of the op Amplifier.

answered Jun 07 '20 at 09:06

Wingman Leee

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Can you explain what "the capacitor C is nearly cut off" means? – Circuit fantasist Jun 07 '20 at 09:54
As time went by, The capacitor C was gradually charged fully, So there's no current flow through the Capacitor. Actually, The feedback loop of op amplifier was open then. So the virtual grounding doesn't stand anymore. – Wingman Leee Jun 08 '20 at 03:55

score 0 · Answer 6 · answered Jun 07 '20 at 05:50

This ubiquitous circuit can be explained in many ways... and all they will be true. But what is important here, is to show the meaning of all this in a clear way... to ask the question, "What does the op-amp really do here?"

Well, it keeps a steady virtual ground... but how does it do this magic? Virtual ground is an abstract concept for beginners. Then can we explain the circuit operation without it? It would be useful for you to see how I have done it in another answer to the same question:

https://electronics.stackexchange.com/a/502087/61398

Horror Vacui · Answer 7 · 2020-06-07T12:12:37.167

The virtual ground is generated by the gain of the feedback loop. If the output of the amplifier saturates, it can't provide any gain and thus the virtual ground collapses.

If no gain is present, then leakage currents will define the voltages. The leakage current might even come from parasitic devices which are not shown in the schematic.

My explanation of rising to 0.65V and then to 1V: The fact that it reaches 0.65 very fast, indicates that a diode starts to clamp it. The JFETs use pn junctions to modulate the cross section of a resistive channel and therefore pn junctions are present between the gate and the source/drain. The current flowing into the non-inverting terminal is due to such reverse bias current of the pn junction. This current flows downwards and increases the voltage at the drain of the input JFET very fast in the beginning, because the bottom current mirror is deactivated. As soon as this voltage approaches the threshold voltage of the mirror's beta helper transistor (0.6-0.7V), the helper starts to conduct current and the base voltage of the mirror starts to raise. As a consequence the mirror will conduct current and swallows the leakage current of the input JFETs gate-drain junction. It is a negative feedback and it will stabilize itself, what the oscilloscope has shown us as well.

Op-Amp Integrator's virtual ground

7 Answers7