1

I am working in verification and my boss came up with a new idea I should be looking into. The verification boards that we are designing for testing the microelectronics that we develop are different each time and we develop them from scratch each time (I take schematic pages from old projects sometimes but I don't reuse boards from older projects).

His new idea is: Build a motherboard that inherits all the generic components that we need for testing in every project and then have a specific board build for the specific chip we have designed in the specific project.

I gotta say I like the idea. I can test some functionality of my test bench before the chips are manufactured and I can reuse these features for other projects. Also digital control which would be programmed from an mcu can be reused.

The chips that we build can be quite different from each other but what they all have in common is that they have similiar voltage supply schemes and they are all configured via spi. So i figure, I could put an mcu as spi-master + the necessary voltage supplies on the motherboard. the "project board" would then be attached to the motherboard with pin-headers(?).

Long story short: What happens to a powersupply rail (lets say 0v8 or 1v8) if I generate it on a motherboard and then transfer it to a 2nd board via a connector (a pin-header/socket-connector for example)? Current won't be that accessible so I would have to provide capacitors on the 2nd board. That I can calculate and come up with capacitors I can place. Is there anything else I should think about? Do you have ideas about this concept? Is there a different connector then pin headers I should consider from your guys opinion?

jkbs1337
  • 11
  • 2
  • 2
    How much current will the boards you are testing need? The answer depends on that to a very large extent. – JRE Jun 02 '20 at 13:05
  • Hello JRE! Let's say I would pull some DC-mA's from the voltagerails. But there could also occur fast switching that would need some pFs to be loaded in few ns... (High Peak Currents). I would supply these with the necessary capacitors as far as I can tell. – jkbs1337 Jun 02 '20 at 13:21

1 Answers1

0

Assume 10nH motherboard PCB + 10nH connector + another 10nH daughterboard PCB + 5nH in package/bondwires (not socket, right/).

Thus your system has to handle 10 + 10 + 10 + 5 = 35 nanoHenries.

Assuming 100 milliAmps switch in 1 nanosecond.

The inductive kick Vbounce = L * dI/dT

  • Vbounce = 35nH * 0.1 amp/1nanoSecond == 3.5 volts.

What size cap? Assume you want only 25 millivolt rail sag.

Using I = C * dV/dT, and rearranging to have C = I * dT / dV

  • C = 0.1 amp * 1nSec / 0.025 volt == (nano) * 0.1/0.025 == 4 nanoFarads at least.

So I suggest the oft-bantered 0.1uF, at least, on your daughterboard.

And why not place a bulk storage cap also, so bursts of clocking don't cause VDD sags on the daughterboard. Remember the 35nH is not your friend.

===================================

I'm glad the 35 nanoHenries makes you nervous, the 3.5 volts is scary, so you decided to place large capacitors very near the IC under test.

Regarding the use of 0.1uF ---- intense switching activity will demand much more charge, as you know. If that is your usage, then LARGE caps are needed. Its your call.

analogsystemsrf
  • 33,703
  • 2
  • 18
  • 46
  • hey! @analogsystemsrf the first calculation wouln't really apply here no? Since im putting Caps close to the demanding chip. And I haven't really understood your thought that goes from 4 to 100. Are you assuming regular switching? – jkbs1337 Jun 03 '20 at 06:32