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If there are multiple ways to get the required clocks for a given CODEC, how do you choose between them?

For example, if a CODEC can accept 64fs, 128fs, 256fs, and has an internal PLL that can generate any of these, why choose one configuration over another?

Lower frequency clocks reduce EMI? Lower frequency clocks draw (slightly) less current? PLLs work better / are more stable / have less jitter when __ is __?

Likewise, if you could choose between two configurations that both work:

  1. DAC MCLK synthesized from SCLK, ADC divided from MCLK
  2. ADC MCLK synthesized from SCLK, DAC divided from MCLK

Why choose one over another? Use the divided MCLK for ADC because it's more stable, and ADC quality is more important than DAC?

In other words, there are multiple possible configurations that work, but what considerations might go into deciding which is best?

endolith
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    very specific to the implementation. a pll may work better with a higher vco for example. You often (if not always) have a range of VCO frequencies as well as other rules you need to follow. Which are not always documented, in part because you have multiple companies involved, multiple departments within at least the chip company, and the eval/demo code works well enough. – old_timer May 28 '20 at 04:45
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    certainly the higher the vco frequency the smaller the period and if the pll could lock on that frequency the the jitter would be smaller, but that assumes the quality of the pll and does it lock that well and can it control the frequency that well at the higher frequency? implementation specific, no general answer. – old_timer May 28 '20 at 04:47
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    I would assume EMI and power are less with a lower VCO frequency but, can you even measure those they are so small. – old_timer May 28 '20 at 04:48
  • @old_timer Yeah I'm not expecting those to be measurable, but couldn't think of anything else. There are requirements on VCO and COMP frequency range, but there are still multiple configurations that meet all requirements. How do I know if higher fVCO results in better performance? – endolith May 28 '20 at 15:46
  • If the chip vendor doesnt say or wont respond to questions then there is no way to know which is "better" even if you take a sample of products and output something clock based and measure jitter that doesnt mean anything across the whole product line. – old_timer May 28 '20 at 16:21
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    I normally lean high, but there is no scientific/technical reason for that. If I were in this situation and there were three choices I would probably take the middle one. and hope for the best, but be prepared for the worst. – old_timer May 28 '20 at 16:21
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    My limited experience would say that "best" relies heavily on the pll and the process/implementation. this cell library on this foundry on this process. someone will have schmoo plots and other data but wont necessarily share that, actually cant imagine them even contemplating sharing that. The better vendor would put some form of documentation be it, with this ref clock and this desired outputs these are the settings or you must divide by between this and that or the vco must be between here and there. Now granted charts in public docs are not always, if ever, made by the – old_timer May 28 '20 at 16:24
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    A-team, so you may end up with the intern and a calculator app on their smart phone with no care in the world about design guidelines, I gotta date this afternoon I gotta get outa here lets bang out this table. Il write a python script, two minutes max...done. folks on the software team have info direct from the chip team not from their docs, so their code may work and yours doesnt. so even if you worked there, you might not have a best answer. – old_timer May 28 '20 at 16:26
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    somebody there knows. you even have situations well if we limit the pll to this range then our yield is this, if we make it tighter our pll is much more reliable but our yield is this, and then some non-technical math/guessing/coin tosses happen and you get what you get the screening doesnt do a lot of testing it relies on schmoo plots over process variants. And you are always expected to have some number of parts fail per 100000 or million. – old_timer May 28 '20 at 16:29
  • (sadly more than once where I work we have dealt with the pll in particular being the reason for a chip spin) – old_timer May 28 '20 at 16:30
  • @old_timer haha ok. Well the datasheet does say "VCO must be between here and there" etc, but those restrictions can be met by multiple configurations. And I have asked the chip maker for advice, so I guess that's all I can do, and I'll see what they say. I'm predicting that they will say there's no difference... – endolith May 28 '20 at 18:48

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