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i'm trying to design a RC filter to drive the ADC of the micro-controller LPC1768 circuit and i need to know the acquisition time of it (which is not in the datasheet). I'm using this article as a design guide. Thank you. Regards

  • It's not just one clock cycle of the ADC clock frequency is it? It's difficult to imagine how a SARS ADC could work with a sampling time shorter than the clock that is clocking its logic. That doesn't rule out the ADC waiting for multiple clock cycles to sample though, but I don't see how it could be shorter than a clock cycle. Check the manual. Maybe you can set the ADC's acquisition time and that's why it is not in the Electrical Specifications. UPDATE: I checked. It's not. – DKNguyen May 11 '20 at 23:45
  • There is more information in user manual https://www.nxp.com/docs/en/user-guide/UM10360.pdf -- though so far I'm not finding timing information about the ADC track/hold timing. – MarkU May 11 '20 at 23:45
  • By the way, there is a technical note about proper PCB layout of the ADC inputs https://www.nxp.com/docs/en/supporting-information/TN00009.pdf though that doesn't address the question about acquisition time. – MarkU May 11 '20 at 23:46
  • The closest thing I found was in the manual under "*29.5.1 A/D Control Register*" in the description for CLKDIV: "*but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.*" – DKNguyen May 11 '20 at 23:51
  • Yes, i was searching in all those places and nothing about acquisition time. This is weird, because usually is a common measurement in datasheets according to sources that i check. – niñoenvuelto May 12 '20 at 00:50
  • Maybe it's too embarrassing to publish. – DKNguyen May 12 '20 at 02:47

1 Answers1

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The datasheet clearly states the max Data Acquisition rate is 200kHz and the article clearly states the maximum bandwidth as 100kHz.

  • Section 8.14 "The LPC17xx contain a single 12-bit successive approximation ADC with eight channels and DMA support,... 12-bit conversion rate: 200 kHz."

Acquisition & setup time is the Sample & Hold time which is normally neglected with very small sampling caps with low leakage in cap and OA to sustain voltage during the sample without drift, so on SAR devices < 10MHz, it is normally ignored. The article refers to a different type of SigMa Delta ADC.

The article is using the maximum Nyquist Rate = 1/2 f_s.

It only shows excellent THD with signals up to 75kHz and tries to compute a simple 1st order filter to achieve setting to <=1 bit for a 12 bit ADC.

The concern is the author neglects the alias distortion for signal >= the Nyquest BW and the filter is only 20 dB /decade with a 66 dB full scale range.

To design the filter you must define the ADC signal Spectral BW i.e. the max amplitude at max frequency or max step size and then max aliasing error allowed.

You might need an 8th order low pass filter with -60 dB at 100kHz using a 75kHz LPF 8th order filter. This is just a Quad Op-Amp using a TI or Falstad analog filter design using 8 caps and N resistors.

For zero aliasing error and full scale 12 bit step input the spectrum of the signal at 100kHz must be <=-66 dB for a low freq. signal defined as 0 dB. Thus a higher order filter is desired rather than a a 1st order RC filter in order to increase the -3dB break point. A 1st order filter would be -60dB at 3 decades below 100kHz or 100Hz which is poor for BW. Therefore we look at the spectrum of a square wave which is ~ -19dB on the 9th harmonic and thus the max rise time without cause aliasing error from an input analog MUX. Otherwise, it's valid for a single channel sine waves only up 75kHZ.

In Conclusion, you need to define the distortion either in terms of max signal frequency, amplitude slew rate or THD. The author neglects aliasing distortion and confines the design to 75kHz maximum sine waves and no stepped MUX signals allowed.

Bottom Line

Given you didn't read the ADC spec carefully in Section and yet show an Analog Mux with 10 channels, if you wanted to avoid adjacent channel interference due to aliasing , you might want to reconsider what accuracy you need. With 10 channels and 200 kHz sampling rate, you get a best case sampling rate of 20 kHz, you will have to restrict your signal BW to about 2kHz max with a 50kHz 8th order LPF.. If your sensors are very low BW, you can scale everything above down.

Tony Stewart EE75
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  • Thanks for your answer. I have a few questions. The first one. Are you assuming the conversion frequency as acquisition frec? this could be a mistake according to this information [link](https://microchipdeveloper.com/adc:adc-acquisition-time). The second one, section 10 of the ADC datasheet are thermal characteristics. What i supposed to see here? maybe i'm missing something. – niñoenvuelto May 12 '20 at 22:40
  • sorry I used a different datasheet...... Sect 8. The article applies only to Sigma Delta – Tony Stewart EE75 May 12 '20 at 23:00
  • Ok, but we are still talking about conversion time and not acquisition time... – niñoenvuelto May 13 '20 at 00:24
  • 200kHz = single channel conversion time = sample rate max, don't confused terms in the SD ADC article for this SAR ADC – Tony Stewart EE75 May 13 '20 at 00:27
  • Did you check this information -> https://microchipdeveloper.com/adc:adc-acquisition-time? – niñoenvuelto May 13 '20 at 00:33