Pass parameters to covergroups in SV Testbench

Question

I am trying to create a parameterized covergroup in my testbench as follows:

covergroup CG (input int id); 

    cp1 : coverpoint tb.gen_block_mem[id].var_x[3:0];

endgroup : CG 

CG CG_0  = new(0);
CG CG_1  = new(1);

This fails in elaboration as the id variable is not a constant. Is there a SystemVerilog workaround for this so that I can instantiate covergroups just like parameterized modules?

score 2 · Accepted Answer · answered May 11 '20 at 20:25

Assuming tb.gen_block_mem is a generate block, you'll have to put the covergroup in another generate block

for(genvar id=0;id<MY_P;id++) begin : cg_block
 covergroup CG; 
  cp1 : coverpoint tb.gen_block_mem[id].var_x[3:0];
 endgroup : CG 
 CG cg  = new;
end : cg_block

Pass parameters to covergroups in SV Testbench

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