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I'm looking at the differential non-linearity specification for an Analog-Digital converter. The spec sheet claims that the DNL ranges from -1LSB to +1LSB, with a typical value of \$\pm\$0.6LSB. What exactly does that mean? Is this some value that's taken statistically? Does this mean the 3 \$\sigma\$ value is 0.6LSB? I.E., for any given code, the range of voltages over which it has jurisdiction is 99.7% likely to be no greater than 1.6LSB or less than 0.4LSB?

Suppose I wanted to model a 16-bit ADC with these specifications. How would I go about injecting DNL into the output codes? The spec sheet is completely unclear as to what 0.6LSB means. Is there some statistical convention? Or would it just be some random number which caps at \$\pm\$1LSB for every single code?

john morrison
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  • "Typical" data are measured on a small number of devices on one of the first lots built, prior to release, as the applications engineer is writing the datasheet and evaluating the device performance. "Min/Max" limits are guaranteed test limits (with some additional guardband against measurement error). See https://electronics.stackexchange.com/a/277525/35022 – MarkU May 01 '20 at 21:03
  • Can you provide link (or at least manufacturer / part number) of the specific ADC you are asking about? Otherwise the question is kind of vague without being able to see the datasheet you're asking about. – MarkU May 01 '20 at 21:05
  • https://www.analog.com/media/en/technical-documentation/data-sheets/AD9461.pdf is the ADC spec sheet I am looking at. From your previous comment you seem to indicate that, if the absolute value of the DNL is no greater than 1LSB, then we are guaranteed, for any two codes, \$V_{C_{n}} - V_{C_{n-1}} \leq 2LSB\$ where \$V_{C_{n}}\$ is the input voltage corresponding to digital output code \$C_n\$ – john morrison May 01 '20 at 21:08
  • +/-1LSB means that some steps may be as small as 0 LSB and some may be as much as 2 LSB, but because no step can be less than 0 LSB it is equivalent to a guarantee the ADC is monotonic. To model it I would suggest a random distribution with mean 0, deviation 0.6 LSB but strictly limited to the -1/+1 range (added to the ideal 1 LSB of course) –  May 01 '20 at 22:07
  • Thank you. Exactly what I had in mind! Feel free to add this as answer if you like – john morrison May 01 '20 at 22:46

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DNL may vary as the implanters and etchers and oxide_growers get older on the wafer fab line.

Testing DNL is costly in time. You will have to pay for that time.

analogsystemsrf
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DNL (dynamic non-linearity) tells you that between two contiguous digital values (i.e. 10010000 and 10010001) the ACTUAL analogue voltage difference is not precisely 1 LSb. In your example of -1LSb to +1LSb, it means that the ACTUAL analogue voltage difference that brought about the two conversions could be: -

  • Exactly the same analogue value
  • An analogue difference value equivalent to 2 LSBs

So, if the device was 8 bit and had a full-scale of (say) 10 volts, the perfect gap between contiguous digital values would be 39.0625 mV. In reality and in some places this actual gap may be as low as 0.00000 mV or as high as 78.125 mV.

This picture from here might help: -

enter image description here

Andy aka
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