crystal oscillator as backup (or with sync)

Question

I have a device that generates a 49.152MHz frequency, but depending on its status it can cut it off from time to time. This frequency synchronizes my MCU's audio devices, but it must never be stopped.

Is there a device like this:

Or like this:

Or how can I design a circus to behave like this?

EDIT

Here is a (very simplified) outline of what I should do.

The backup clock generation could be a crystal or (to save money) could be a signal generated by the MCU itself.

If main clock is present the phase between out clock and main clock must be constant, and out clock should have no jitter (or no more than the main clock). When main clock goes off (or UXT is not populated) there should be a transition to backup clock. When main clock returns there should be a transition to it.

However jitter on clock out is not a problem compared to what the phase would be. I'm doing all this to synchronize everything with the clock recovered from the Dante stream. It may happen that the 48kHz recovered by Dante and the 48kHz obtained from my micro (and my crystal) have variable phase shift (e.g. one 48001 Hz and the other 47998). Wanting to avoid an ASRC the only solution is to make UXT master of all the clock domains. But we have to deal with the fact that UXT can shut down biefly the clock or it may not be populated (we have boards without Dante's capability), whereas ADC and DAC must always be clocked. Hence the need for a backup clock.

I have some area and cost constraints, so the solution should be not too big and definitely cheap.

This sounds like an XY problem. Why does your clock disappear? — Andy aka, Apr 13 '20 at 11:19
Some SPDIF receivers can do this. What device sources the clock? Can that device be a slave so MCU generates all clocks? — Justme, Apr 13 '20 at 11:21
@Andyaka The clock is generateb by [Audinate Ultimo UXT MCU](https://www.audinate.com/products/manufacturer-products/dante-ultimo). It takes a Dante audio stream over IP and recover the master clock of i2s from that stream. It can disappear because it can be rebooted/updated by an Audinate software the uor customers have to use to configure the Dante network. Unfortunately that master clock must be syncronous to AD/DA TDM8 master clock that are connected to our micro. — mastupristi, Apr 13 '20 at 11:30
@Justme [Audinate Ultimo UXT MCU](https://www.audinate.com/products/manufacturer-products/dante-ultimo) is source of master clock, and it cannot be slave, because it recover that master clock from Dante audio stream that comes from the ethernet. Our micro has to be slave to avoid the use of Asyncronous Sample Rate Converter. — mastupristi, Apr 13 '20 at 11:32
@Hearth because if we use our clock all time we need an Asyncronous Sample Rate Converters. But to maintain low cost and an easy design we must avoid this. The only way is to be slave of the external device. But when this exernal device is not populated or briefly stop to generate it we need a backup clock to get AD/DA to keep working. — mastupristi, Apr 13 '20 at 11:37
Can your micro be configured to use a different *internal* clock source for it's audio AD?DA peripherals? If it can, I'd suggest that you have the micro monitor the state of the 49MHz clock (maybe use a counter as a kind-of watchdog) and have it re-configure when the clock goes missing. — brhans, Apr 13 '20 at 11:43
@brhans unfortunately no. It can be either master or slave of the MCLK, and the MCLK is only one — mastupristi, Apr 13 '20 at 11:50
I found this [patent](https://patents.google.com/patent/US4982116). It sounds like what I need. It's dated 1991, so it's almost 30 years old. Is it possible there's no one who's implemented it into a device? — mastupristi, Apr 13 '20 at 11:52
I recall AKM or Cirrus made audio interface chips that can generate "house clocks" so that they continue clocn generation if input drops. Have you checked these? You may have to regenerate the master clock from bit clock or leftright clock from Dante but at least you will have continuous master clock. — Justme, Apr 13 '20 at 12:29
@justme when Ultimo UXT stop generating MCKL it also stop BitClock and FrameSync. I cannot recover MCLK from them — mastupristi, Apr 13 '20 at 13:11
Exactly, that's why you need the "house clock" chip to switch to generating MCLK from the crystal automatically. — Justme, Apr 13 '20 at 13:19
found [Si5350C](https://www.silabs.com/documents/public/data-sheets/Si5350C-B.pdf) but is quite expensive. However, do what I want — mastupristi, Apr 13 '20 at 15:22

score 1 · Answer 1 · answered Apr 13 '20 at 11:51

1

A Phase-Locked Loop will do this.

https://en.wikipedia.org/wiki/Phase-locked_loop

The simplest phase comparator is an XOR gate. This simplest loop filter is an RC filter. The VCO should be a Voltage Controlled Crystal Oscillator (VCXO).

This circuit will cleanly transition between the clocks, no risk of glitches.

The VCXO may break your budget.

You can find PLL design equations online. Surprisingly, the circuit is easy to make stable.

answered Apr 13 '20 at 11:51

Mattman944

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I'm sorry, but I don't know what you mean. You say: _"This circuit will cleanly transition between the clocks, no risk of glitches."_ and I like that very much. I just don't see how to connect my `main clock` and `backup clock`. – mastupristi Apr 13 '20 at 12:00
Your main clock connects on the left side. The VCXO is the backup clock. – Mattman944 Apr 13 '20 at 12:01
Why do you say surprisingly about its stability? – Hearth Apr 13 '20 at 12:27
Audio interface chips and DSPs that have VCXOs inside them do exist already. No need to manually design a VCXO. – Justme Apr 13 '20 at 12:32
@Hearth - most circuits with feedback can go unstable fairly easily, this will not. – Mattman944 Apr 13 '20 at 13:22
@Mattman944 when the main clock is present I need the clock out to be fixed phase and no jitter with respect to main clock. Is that guaranteed? When main clock is not present where is applied the crystal-oscillator clock? – mastupristi Apr 13 '20 at 13:42
@mastupristi - all clocks have some jitter. The PLL will add some jitter since it is locking onto the main clock. If jitter is critical, you will need to complete the design and analyze it. – Mattman944 Apr 13 '20 at 14:15
@Mattman944 jitter is not a problem compared to what the phase would be. It may happen that the 48kHz reconstructed by Dante and the 48kHz obtained from my micro (and my crystal) have variable phase shift (e.g. one 48001 Hz and the other 47998). Wanting to avoid an ASRC the only solution is to make UXT master of all the clock domains. But we have to deal with the fact that UXT can shut down biefly the clock or it may not be populated (we have cards without Dante's capability), whereas ADC and DAC must always be clocked. Hence the need for a backup clock. – mastupristi Apr 13 '20 at 14:32
@Mattman944 what happens in your scheme when the `main clock` is down? – mastupristi Apr 13 '20 at 14:41
In the PLL that I described, the VCXO always runs at a frequency very close to the crystal frequency in the VCXO. A VCXO can only vary the frequency of a crystal a small amount (a few hundred ppm typically). In the absence of a main clock the XOR and filter will output a voltage of about 1/2 VCC causing the frequency to be near the center point of the VCXO. When the main clock is present, the PLL will lock onto it. This simple phase comparator will not have a zero phase shift, but it should be constant if the main clock is perfectly stable. – Mattman944 Apr 13 '20 at 16:43

score 0 · Answer 2 · answered Apr 13 '20 at 12:49

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I think you are looking for AK4115 or very similar chip. It can either generate the master clock from it's crystal oscillator, or output a PLL-generated master clock by using LRCLK as input reference. At least you can get a warning when the PLL unlocks or clocks switch.

answered Apr 13 '20 at 12:49

Justme

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AK4115 is a Transceiver. I eventually need only a little slice of it. My micro is NXP RT1051. It has SAI peripheral that are multi channel audio interface. the SAIs support i2s and TDM stream. Ultimo UXT is another chip that is master on two i2s channel. I don't think that AK4115 can help me – mastupristi Apr 13 '20 at 13:22
A design I once saw only used that little part inside it to generate continuous clocks. It may not have been this exact same part but very similar, like I mentioned. If it does the job, by generating continuous master clock either from crystal or unreliably available LRCK, then it does the job you asked in the question. So why can't you utilize this, if it seems to do the job? – Justme Apr 13 '20 at 13:34
beacuse it is a big chip, and I have area constraits. Because it is quiite expensive withe respect to the function I would use for. – mastupristi Apr 13 '20 at 13:39
OK. Then perhaps edit size and cost restrictions to the question, to avoid people suggesting too big and expensive solutions, because we can't know the limitations. – Justme Apr 13 '20 at 13:45

score 0 · Answer 3 · answered Apr 13 '20 at 16:53

The 74HC123 is a re-triggerable monostable oscillator. Set the pulse duration at 150% of the desired timeout, so there is tolerance for temperature variations and VDD changes.

Using the monostable (ake oneshot), you have a "the clock died" detector.

Use that output, or the inverted output, to control a multiplexor. Or make your own digital multiplexor, using 3 NAND gates.

crystal oscillator as backup (or with sync)

EDIT

3 Answers3