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Many years ago, I found a digital circuit that squares a 4-bit input in an old textbook (perhaps 1970s or 1980s, possibly older).
(The figure below is not the original figure.
I think the figure below differs from the original in that it has been rotated 90 degrees.)
I do not have access to that textbook any more and I do not have additional details about the textbook.

Have you seen this circuit before?
If so, could you give me the name and author of the source?
I am using this figure in my teaching and I would like to properly cite the source.

Squarer

greybeard
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JRN
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    In passing, found this paper which might interest you https://pdfs.semanticscholar.org/29f0/132fbbc51ef05c2f1c9e732cafe93286160d.pdf – jonathanjo Mar 19 '20 at 15:32
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    And United States Patent RE35365 from 1996 http://www.freepatentsonline.com/RE35365.pdf and 5,629,885 from 1997 https://patentimages.storage.googleapis.com/70/87/c7/7dd3a18b9b2882/US5629885.pdf – jonathanjo Mar 19 '20 at 19:40
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    the schematic may have originated from a device datasheet – jsotola Mar 20 '20 at 00:53
  • @jonathanjo, thank you for the links. I'm not familiar with them, and they look very useful. – JRN Mar 20 '20 at 01:20
  • @jsotola, if you find a data sheet that has this circuit, then please add it as an answer. Thanks. – JRN Mar 20 '20 at 01:21

1 Answers1

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A derivation instead of an identification:

bit-wise partial products:                  A₃A₀         A₂A₀  A₁A₀ A₀A₀
                                A₃A₁        A₀A₃         A₀A₂  A₀A₁
                  A₃A₂          A₁A₃        A₂A₁         A₁A₁
     A₃A₃         A₂A₃          A₂A₂        A₁A₂
simplification:                                                   0  A₀
                                A₃A₀        A₂A₀         A₀A₁
     A₃A₂         A₃A₁          A₂A₁                      A₁
      A₃                         A₂

circuit (from Q):
horizontal 4-bit squarer

7400-series implementation:
As sketched, 2×'08, 3×'183 for lack of half-adders. Or 2×'183, 1×'86, same total of 5×14 pin.

More likely to be around would be '(2)83 4-bit adders.
Without a carry in, you can use "same significance 2k" inputs Ak and Bk "as an and gate":
There will be a carry out (to k+1) iff both are true.
Pulling off this trick twice reduces the BOM to 1×'08, 2×'283 for a total of 46 pins.

(Better presentation options than Falstad?)

The MSB of the square is just the AND of both most significant input bits.
Bit S₂ is somewhat simple: A1¬A0, but those middle bits are just too complicated for (me to find a?) slick '7400 implementation.

greybeard
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