I am having issue with AXI Protocol Checker pc_status[22] AXI_ERRM_WSTRB .
Write strobes must only be asserted for the correct byte lanes as determined from the: Start Address, Transfer Size and Beat Number.
What does it mean by The information on the low-order address lines must be consistent with the information on the byte lane strobes. ?
The problem is with your combination of the write address and the write strobes.
Your write addresses are 1,2,3.
But at the same time your write strobes are 0xFFFF thus all 16 byte lines are active. That is not allowed with the addresses of 1,2,3. The first 1, 2 and 3 byte strobes must be zero because you address is skipping those bytes.
See figure A3-13 on page A3-57 of the AXI document your refer to.
Coming back to your addressing:
Your write addresses are 1,2,3. (I can't see the first one, I assume it to be zero). That by itself is not illegal but it is weird. Normally on a 128 bit wide bus you would have the bottom 4 address bits always at zero. Thus increment by at least 16 (0x10) Are you sure that is what you want?
Next weird thing I notice is that you seem to write in bursts, but I don't know how long they are. The relevant signal are missing from your waveform.
However with 16 byte wide data and e.g. a burst of 16 your next address should be 16x16=256 addresses further on. But it is one!
